Custom IC Design

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convergence issue

Category: Custom IC Design

By IcoNem

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updated over 7 years ago by Andrew Beckett

1 replies • 30448 views
Discussion

is there any way that we can run lvs with schematic in OA virtuoso version 6.1.6-64b and layout in icfb 5.1.0

Category: Custom IC Design

By Nhumai

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updated over 7 years ago by Nhumai

7 replies • 16766 views
Discussion

How to check to see if we have Voltus license >

Category: Custom IC Design

By Nhumai

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updated over 7 years ago by Nhumai

4 replies • 2102 views
Discussion

verilog-a model help

Category: Custom IC Design

By SatendraMaurya

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updated over 7 years ago by SatendraMaurya

12 replies • 17922 views
Discussion

Loading bindkeys

Category: Custom IC Design

By skillEater

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updated over 7 years ago by skillEater

5 replies • 16247 views
Discussion

Virtuoso 6.1.7 ADE XL always pending...

Category: Custom IC Design

By Big fish

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updated over 7 years ago by Big fish

7 replies • 17970 views
Discussion

SPECTRE SP analysis -- noise correlation matrix

Category: Custom IC Design

By Yevgeny

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updated over 7 years ago by Andrew Beckett

2 replies • 2462 views
Discussion

Output busses containing shared nets yielding an error

Category: Custom IC Design

By CADcasualty

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updated over 7 years ago by CADcasualty

8 replies • 20155 views
Discussion

how to rename all the cell in the standard cell library by scripts?

Category: Custom IC Design

By enzhu

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updated over 7 years ago by Andrew Beckett

1 replies • 17169 views
Discussion

DC op point from an S-parameter Analysis

Category: Custom IC Design

By Curtisma

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updated over 7 years ago by Andrew Beckett

1 replies • 15355 views
Discussion

Bsource tutorial

Category: Custom IC Design

By IcoNem

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updated over 7 years ago by Andrew Beckett

2 replies • 20036 views
Discussion

Error "version `GLIBCXX_3.4.15' not found" when running PVS LVS in command line

Category: Custom IC Design

By Mamad

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updated over 7 years ago by Mamad

2 replies • 1811 views
Discussion

how to report net names connected to transistors for a channel connected block

Category: Custom IC Design

By SatendraMaurya

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updated over 7 years ago by SatendraMaurya

4 replies • 14942 views
Discussion

Problems generating layout

Category: Custom IC Design

By rafaelon

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updated over 7 years ago by monkeydliren

4 replies • 18769 views
Discussion

calibreview fatal error

Category: Custom IC Design

By CxD7

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updated over 7 years ago by Andrew Beckett

6 replies • 23475 views

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