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Custom IC Design

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  • Discussion

    Issue with Level=3 MOS model in Spectre

    Category: Custom IC Design

    By milind123 milind123

    •

    updated 3 months ago by milind123

    16 replies • 2981 views
  • Discussion

    Cross-hierarchy control of node voltage?

    Category: Custom IC Design

    By dogman4 dogman4

    •

    updated 3 months ago by dogman4

    2 replies • 1176 views
  • Discussion

    When I was liberating a DFF cell that has three outputs {Q QN Q1},I get the trouble

    Category: Custom IC Design

    By TH20240830782 TH20240830782

    •

    updated 3 months ago by Guangjun Cao

    1 replies • 444 views
  • Discussion

    2 tests sim with different temperature

    Category: Custom IC Design

    By dogman4 dogman4

    •

    updated 3 months ago by dogman4

    2 replies • 1213 views
  • Discussion

    The spec of adexl

    Category: Custom IC Design

    By dogman4 dogman4

    •

    updated 3 months ago by dogman4

    3 replies • 1388 views
  • Discussion

    Spectre error: parameter range violation

    Category: Custom IC Design

    By TM202409102328 TM202409102328

    •

    updated 3 months ago by Andrew Beckett

    1 replies • 1244 views
  • Discussion

    run plan - pass a filepath though the calcVal() function

    Category: Custom IC Design

    By cnicola cnicola

    •

    updated 3 months ago by cnicola

    1 replies • 377 views
  • Discussion

    creating output expression while doing parametric sweep

    Category: Custom IC Design

    By Svilen64 Svilen64

    •

    updated 3 months ago by Volker T

    1 replies • 1279 views
  • Discussion

    Setting supply sensitivity by default for any new pin in Virtuoso Schematic

    Category: Custom IC Design

    By MN202411268924 MN202411268924

    •

    started 3 months ago

    0 replies • 972 views
  • Discussion

    Set Use No DM option to default when create library in library manager

    Category: Custom IC Design

    By JH202504237643 JH202504237643

    •

    started 3 months ago

    0 replies • 1057 views
  • Discussion

    metal pin in layout is showing its actual color

    Category: Custom IC Design

    By rtyuy rtyuy

    •

    updated 3 months ago by rtyuy

    7 replies • 2050 views
  • Discussion

    Aging Simulation Failure.(success in HCI mode, failure in PBTI mode and NBTI mode)

    Category: Custom IC Design

    By LS202412014215 LS202412014215

    •

    started 3 months ago

    0 replies • 995 views
  • Discussion

    import verilog

    Category: Custom IC Design

    By MS202504187741 MS202504187741

    •

    updated 4 months ago by MS202504187741

    1 replies • 1446 views
  • Discussion

    ERROR (SFE-874). Not able to resolve this issue

    Category: Custom IC Design

    By akaraguppi akaraguppi

    •

    updated 4 months ago by akaraguppi

    2 replies • 1539 views
  • Discussion

    Importing Synopsys .slib symbols to Cadence Virtuoso

    Category: Custom IC Design

    By rajasnene16 rajasnene16

    •

    updated 4 months ago by rajasnene16

    2 replies • 1394 views
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