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Custom IC Design

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  • Discussion

    Is it possible when schematic changes in virtuso can I get some alarm or alert?

    Category: Custom IC Design

    By shane park

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    •

    updated over 2 years ago by shane park

    2 replies • 6144 views
  • Discussion

    Check VCO oscillating in transient and PSS

    Category: Custom IC Design

    By lswei1984

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    •

    updated over 2 years ago by ShawnLogan

    1 replies • 6694 views
  • Discussion

    Noise Summary per Instance

    Category: Custom IC Design

    By illaoi

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    •

    updated over 2 years ago by Andrew Beckett

    5 replies • 8183 views
  • Discussion

    NO DC solution found(No convergence) when use ADEXL,but use ADEL is right.

    Category: Custom IC Design

    By SpiceHusky

    $usertype

    •

    updated over 2 years ago by Andrew Beckett

    3 replies • 1958 views
  • Discussion

    Spectre warning: there are some nodes and instances from the netlist topology check.

    Category: Custom IC Design

    By ppptt

    $usertype

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    updated over 2 years ago by Andrew Beckett

    1 replies • 6814 views
  • Discussion

    PVS fails with version `GLIBCXX_3.4.26' not found

    Category: Custom IC Design

    By thspaet

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    •

    updated over 2 years ago by thspaet

    3 replies • 3140 views
  • Discussion

    setting cell's view in config as dynamic parameter

    Category: Custom IC Design

    By sjwprcker

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    •

    updated over 2 years ago by sjwprcker

    2 replies • 1358 views
  • Discussion

    BJT models HiCUM (bht)

    Category: Custom IC Design

    By sidm

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    updated over 2 years ago by sidm

    6 replies • 8001 views
  • Discussion

    DRC check and LVS check has no error but still seeing the layer error?

    Category: Custom IC Design

    By Vishesh Gupta

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    updated over 2 years ago by Andrew Beckett

    1 replies • 6101 views
  • Discussion

    Setting dynamic parmeter in pss analysis

    Category: Custom IC Design

    By Abhrarup

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    •

    updated over 2 years ago by Andrew Beckett

    1 replies • 6205 views
  • Discussion

    Maestro : Width of columns in "Results" Tab is large. How to reduce it?

    Category: Custom IC Design

    By Saikiran IND

    $usertype

    •

    updated over 2 years ago by Saikiran IND

    2 replies • 1475 views
  • Discussion

    Maestro: Simulation Settings as Output Expressions

    Category: Custom IC Design

    By Saikiran IND

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    •

    updated over 2 years ago by Saikiran IND

    2 replies • 6800 views
  • Discussion

    The region of operation of MOS transistor

    Category: Custom IC Design

    By PhD Student

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    •

    updated over 2 years ago by PhD Student

    12 replies • 13490 views
  • Discussion

    Simulation startup is too slow

    Category: Custom IC Design

    By Firdos

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    •

    updated over 2 years ago by ShawnLogan

    1 replies • 6561 views
  • Discussion

    rexMatchp error when netlist

    Category: Custom IC Design

    By sjwprcker

    $usertype

    •

    updated over 2 years ago by Andrew Beckett

    1 replies • 6592 views
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