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Custom IC Design

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  • Discussion

    Grid spacing for 45nm GPDK process

    Category: Custom IC Design

    By madhanmo

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    started over 11 years ago

    0 replies • 13582 views
  • Discussion

    How to eliminate unused empty cells when importing GDS

    Category: Custom IC Design

    By marklin

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    started over 11 years ago

    0 replies • 13442 views
  • Discussion

    pipo.log and strmOut.log

    Category: Custom IC Design

    By radiowaves

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    updated over 11 years ago by radiowaves

    2 replies • 15192 views
  • Discussion

    XL Layout issue with custom Library layout sourcing the Schematic.

    Category: Custom IC Design

    By JP Layout

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    started over 11 years ago

    0 replies • 12778 views
  • Discussion

    freeze with virtuoso layout

    Category: Custom IC Design

    By Fabb

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    updated over 11 years ago by Andrew Beckett

    1 replies • 15023 views
  • Discussion

    do stb analysis on five stage invter ring osc

    Category: Custom IC Design

    By xianweng

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    updated over 11 years ago by xianweng

    3 replies • 14489 views
  • Discussion

    Unable to run Monte Carlo ADEXL-1723

    Category: Custom IC Design

    By Faizalism

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    updated over 11 years ago by Andrew Beckett

    3 replies • 13567 views
  • Discussion

    How to do a parametric analysis for a model parameter ?

    Category: Custom IC Design

    By Ahmed Taha

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    updated over 11 years ago by FormerMember

    2 replies • 15002 views
  • Discussion

    How to define a binary matrix parameter in Verilog A

    Category: Custom IC Design

    By microstudent

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    updated over 11 years ago by microstudent

    6 replies • 22757 views
  • Discussion

    RLGC matrix size does not match between instance and model 'mtline'

    Category: Custom IC Design

    By SUEE

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    updated over 11 years ago by SUEE

    2 replies • 7411 views
  • Discussion

    How to set bindkeys of Virtuoso alignment window

    Category: Custom IC Design

    By microstudent

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    •

    started over 11 years ago

    0 replies • 14470 views
  • Discussion

    Spectremdl and Verilog-A variable

    Category: Custom IC Design

    By dan9876

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    started over 11 years ago

    0 replies • 12795 views
  • Discussion

    STD cell characterization

    Category: Custom IC Design

    By Sharif H N

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    updated over 11 years ago by Quek

    1 replies • 13363 views
  • Discussion

    ERROR (SPECTRE-8390): Problem encountered in setting up the mpsc front end.

    Category: Custom IC Design

    By admin

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    updated over 11 years ago by ArthurLombardi

    3 replies • 14740 views
  • Discussion

    CDR for USB 3.0 PHY

    Category: Custom IC Design

    By Jithin

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    updated over 11 years ago by Jithin

    2 replies • 14221 views
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