Custom IC Design

Latest Posts

Discussion

Use instance name for design variable in schematic

Category: Custom IC Design

By ZipppyDoctor

$usertype
•
started over 3 years ago

0 replies • 7862 views
Discussion

Calculator: How to avoid interpolation when using spectrumMeasurement()?

Category: Custom IC Design

By jorgeluislagos

$usertype
•
updated over 3 years ago by jorgeluislagos

4 replies • 9769 views
Discussion

Is there any documentation for PVS DRC rules writting?

Category: Custom IC Design

By delgsy

$usertype
•
updated over 3 years ago by delgsy

2 replies • 9878 views
Discussion

replace square bus notation brackets with < and >

Category: Custom IC Design

By pula58

$usertype
•
updated over 3 years ago by shubhamiitb

1 replies • 2772 views
Discussion

I am trying to simulate a basic ring oscillator circuit using spectra . I have generated a netlist file. when I run it, I am getting the following error: I need help urgently for my thesis

Category: Custom IC Design

By Sudipta

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 8737 views
Discussion

follow up with find the location of a variable in schematic

Category: Custom IC Design

By monglebest2022

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 8591 views
Discussion

How to change default spacing between symbol's pins that auto-created from schematic

Category: Custom IC Design

By SpiceMonkey

$usertype
•
updated over 3 years ago by Andrew Beckett

1 replies • 1646 views
Discussion

DEF formatting

Category: Custom IC Design

By SSR

$usertype
•
updated over 3 years ago by SSR

1 replies • 8412 views
Discussion

Discrepancy in Stability Analysis

Category: Custom IC Design

By Ashish Papreja

$usertype
•
updated over 3 years ago by FormerMember

1 replies • 8809 views
Discussion

adding delay element to circuit

Category: Custom IC Design

By Soly

$usertype
•
updated over 3 years ago by FormerMember

1 replies • 12002 views
Discussion

calculator plot function fail

Category: Custom IC Design

By sjwprcker

$usertype
•
updated over 3 years ago by FormerMember

1 replies • 8550 views
Discussion

SystemVerilog generate loop does not compile modules defined inside loop

Category: Custom IC Design

By Nader Fathy

$usertype
•
updated over 3 years ago by SimbaG

2 replies • 11363 views
Discussion

Dc level shifter

Category: Custom IC Design

By Khaleed01

$usertype
•
updated over 3 years ago by FormerMember

3 replies • 10199 views
Discussion

Alter Device Parameter when Device is in Array

Category: Custom IC Design

By Jeff Kauppila

$usertype
•
started over 3 years ago

0 replies • 7803 views
Discussion

How to simulate (equivalent) noise (charge) of CSA?

Category: Custom IC Design

By delgsy

$usertype
•
started over 3 years ago

0 replies • 8036 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.