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Functional Verification

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  • Discussion

    How do I update a 'test case' attribute in a vPlan using the vManager API (vAPI)

    Category: Functional Verification

    By Sean Collins

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    updated over 5 years ago by Sean Collins

    3 replies • 5098 views
  • Discussion

    When to ideally run an UNR Analysis?

    Category: Functional Verification

    By sumg

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    •

    started over 5 years ago

    0 replies • 15178 views
  • Discussion

    Conformal Litmus vs JasperGold CDC

    Category: Functional Verification

    By ChrisKAustin

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    updated over 5 years ago by ChrisKAustin

    2 replies • 17193 views
  • Discussion

    The Best Way to Learn SystemVerilog Accelerated Verification with UVM – Blended Training

    Category: Functional Verification

    By SAIKAT SANA

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    started over 5 years ago

    0 replies • 15189 views
  • Discussion

    Prevent SimVision Schematic Viewer from Re-Zooming/Centering after tracing a signal

    Category: Functional Verification

    By Commsolid

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    •

    updated over 5 years ago by Commsolid

    2 replies • 4111 views
  • Discussion

    VManager + DRM user specific config (HTCondor)

    Category: Functional Verification

    By BGarcia

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    •

    updated over 5 years ago by StephenH

    6 replies • 19079 views
  • Discussion

    executing ncsim commands from verilog using system task

    Category: Functional Verification

    By Arturi

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    updated over 5 years ago by StephenH

    3 replies • 18154 views
  • Discussion

    Xcelium: Altering return value of $temperature in digital simulation

    Category: Functional Verification

    By MartinJ

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    updated over 5 years ago by MartinJ

    2 replies • 16519 views
  • Discussion

    fatal voltage source/inductor loop

    Category: Functional Verification

    By Ben321

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    •

    started over 5 years ago

    0 replies • 2689 views
  • Discussion

    vAPI filter return no duplciate

    Category: Functional Verification

    By yPerrot

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    •

    updated over 5 years ago by yPerrot

    2 replies • 15399 views
  • Discussion

    SystemVerilog EEnet input driven by current source

    Category: Functional Verification

    By HoWei

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    started over 5 years ago

    0 replies • 15892 views
  • Discussion

    Instantiate SystemC module in SystemVerilog module with real/double ports

    Category: Functional Verification

    By coderoo

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    •

    started over 5 years ago

    0 replies • 4625 views
  • Discussion

    e code coverage

    Category: Functional Verification

    By aefody

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    •

    updated over 5 years ago by aefody

    2 replies • 15859 views
  • Discussion

    Analog circuit designing

    Category: Functional Verification

    By Meer

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    •

    started over 5 years ago

    0 replies • 14445 views
  • Discussion

    [JasperGold] Behavioral Analysis - How to exercise it properly?

    Category: Functional Verification

    By Murilo Santos

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    •

    started over 5 years ago

    0 replies • 1549 views
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