• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Functional Verification
CDNS - double leaderboard script

Functional Verification

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Latest Posts

  • Create a new Post
  • Discussion

    VManager + DRM user specific config (HTCondor)

    Category: Functional Verification

    By BGarcia

    $usertype

    •

    updated over 5 years ago by StephenH

    6 replies • 18497 views
  • Discussion

    executing ncsim commands from verilog using system task

    Category: Functional Verification

    By Arturi

    $usertype

    •

    updated over 5 years ago by StephenH

    3 replies • 17641 views
  • Discussion

    Xcelium: Altering return value of $temperature in digital simulation

    Category: Functional Verification

    By MartinJ

    $usertype

    •

    updated over 5 years ago by MartinJ

    2 replies • 16079 views
  • Discussion

    fatal voltage source/inductor loop

    Category: Functional Verification

    By Ben321

    $usertype

    •

    started over 5 years ago

    0 replies • 2649 views
  • Discussion

    vAPI filter return no duplciate

    Category: Functional Verification

    By yPerrot

    $usertype

    •

    updated over 5 years ago by yPerrot

    2 replies • 15000 views
  • Discussion

    SystemVerilog EEnet input driven by current source

    Category: Functional Verification

    By HoWei

    $usertype

    •

    started over 5 years ago

    0 replies • 15496 views
  • Discussion

    Instantiate SystemC module in SystemVerilog module with real/double ports

    Category: Functional Verification

    By coderoo

    $usertype

    •

    started over 5 years ago

    0 replies • 4514 views
  • Discussion

    e code coverage

    Category: Functional Verification

    By aefody

    $usertype

    •

    updated over 5 years ago by aefody

    2 replies • 15467 views
  • Discussion

    Analog circuit designing

    Category: Functional Verification

    By Meer

    $usertype

    •

    started over 5 years ago

    0 replies • 14093 views
  • Discussion

    [JasperGold] Behavioral Analysis - How to exercise it properly?

    Category: Functional Verification

    By Murilo Santos

    $usertype

    •

    started over 5 years ago

    0 replies • 1484 views
  • Discussion

    generate over a loop the same module with different parameter and maintain it in systemverilog UVM environment

    Category: Functional Verification

    By EranW

    $usertype

    •

    updated over 5 years ago by EranW

    2 replies • 14378 views
  • Discussion

    Does driver trace through system verilog interfaces ever work?

    Category: Functional Verification

    By ese002b

    $usertype

    •

    updated over 5 years ago by ese002b

    2 replies • 16197 views
  • Discussion

    Lint errors

    Category: Functional Verification

    By parvathyram

    $usertype

    •

    started over 5 years ago

    0 replies • 13988 views
  • Discussion

    irun & ncvlog version conflict

    Category: Functional Verification

    By Zdeno

    $usertype

    •

    updated over 5 years ago by Zdeno

    3 replies • 7566 views
  • Discussion

    Excluding unused functions in JasperGold Superlint

    Category: Functional Verification

    By Max Bjurling

    $usertype

    •

    started over 5 years ago

    0 replies • 14538 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information