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Functional Verification

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  • Discussion

    Systemverilog-2008 and variadic `define macros?

    Category: Functional Verification

    By cubicle82

    •

    updated over 17 years ago by Shalom B

    1 replies • 16046 views
  • Discussion

    Conversion of an Integer port in VHDL to equivalent in Verilog

    Category: Functional Verification

    By Sarvesh

    •

    updated over 17 years ago by cubicle82

    2 replies • 17811 views
  • Discussion

    Verilog Name Collisions - irun v8.1

    Category: Functional Verification

    By Dave123

    •

    updated over 17 years ago by StephenH

    2 replies • 2164 views
  • Discussion

    pointers in sequence items

    Category: Functional Verification

    By kabb

    •

    updated over 17 years ago by Hilmar

    3 replies • 15617 views
  • Discussion

    Insert coverage model table using AutoText

    Category: Functional Verification

    By jnyman

    •

    updated over 17 years ago by StephenH

    1 replies • 14813 views
  • Discussion

    test bridge by eVC

    Category: Functional Verification

    By spark

    •

    updated over 17 years ago by StephenH

    1 replies • 14978 views
  • Discussion

    Verilog-XL install

    Category: Functional Verification

    By bdatta

    •

    updated over 17 years ago by StephenH

    2 replies • 15510 views
  • Discussion

    Calling base class methods

    Category: Functional Verification

    By Walker

    •

    updated over 17 years ago by StephenH

    1 replies • 15019 views
  • Discussion

    cannot run simvision

    Category: Functional Verification

    By bdatta

    •

    updated over 17 years ago by StephenH

    1 replies • 19481 views
  • Discussion

    error when passing a string to ncutils

    Category: Functional Verification

    By JMGGL

    •

    updated over 17 years ago by JMGGL

    13 replies • 22628 views
  • Discussion

    eVC development

    Category: Functional Verification

    By johnrusia

    •

    updated over 17 years ago by teamspecman

    1 replies • 6333 views
  • Discussion

    Profiling the runtime of SystemVerilog Assertions

    Category: Functional Verification

    By danlarkin

    •

    updated over 17 years ago by danlarkin

    4 replies • 19766 views
  • Discussion

    Temporal expression in e

    Category: Functional Verification

    By spark

    •

    updated over 17 years ago by mstellfox

    5 replies • 16234 views
  • Discussion

    AXI EVC user manual

    Category: Functional Verification

    By SandS

    •

    updated over 17 years ago by StephenH

    1 replies • 15460 views
  • Discussion

    Layout Instance Names on VNL Netlists?

    Category: Functional Verification

    By moss

    •

    updated over 17 years ago by tpylant

    1 replies • 14952 views
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