Logic Design

Latest Posts

Discussion

Trouble with reading vcd file in RC 11.2

Category: Logic Design

By Chongxi
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updated over 12 years ago by grasshopper

1 replies • 13116 views
Discussion

RTL Compiler, Min Libraries and CPF

Category: Logic Design

By moogyd
•
updated over 12 years ago by grasshopper

3 replies • 14654 views
Discussion

Synthesis in rclabs using slow and fast library

Category: Logic Design

By Maheshnb
•
updated over 12 years ago by grasshopper

3 replies • 15397 views
Discussion

How to add Synthesizable delay into the module

Category: Logic Design

By Maheshnb
•
updated over 12 years ago by grasshopper

1 replies • 13145 views
Discussion

max_fanout constraint

Category: Logic Design

By tanyacool
•
started over 12 years ago

0 replies • 13112 views
Discussion

how to find out the FFs connected to the output of a selected FF

Category: Logic Design

By gops
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updated over 12 years ago by bmiller

1 replies • 13000 views
Discussion

what dose pulse width mean in timing report

Category: Logic Design

By small5
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started over 12 years ago

0 replies • 13047 views
Discussion

RTL Compiler synthesis commands for TDC design

Category: Logic Design

By Maheshnb
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started over 12 years ago

0 replies • 13096 views
Discussion

RC: to Remove PG pins from a Netlist..

Category: Logic Design

By Yemelya
•
updated over 12 years ago by bmiller

1 replies • 14527 views
Discussion

Groups back annotaion (allegro to concept and back)

Category: Logic Design

By bdv005
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started over 12 years ago

0 replies • 13013 views
Discussion

Wanted to know the behaviour of RC on different SDC command

Category: Logic Design

By tanyacool
•
updated over 12 years ago by tanyacool

2 replies • 14287 views
Discussion

Outputting a synthesized file in reverse order

Category: Logic Design

By Ankur S
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started over 12 years ago

0 replies • 12720 views
Discussion

LEC issue - "elaborate" vs. "synthesize -to_generic"

Category: Logic Design

By Yemelya
•
updated over 12 years ago by bmiller

1 replies • 1520 views
Discussion

-binding flag is ignored by ncelab

Category: Logic Design

By myonlyscreen
•
updated over 12 years ago by TAM1

3 replies • 2952 views
Discussion

area calculation by RC

Category: Logic Design

By tanyacool
•
updated over 12 years ago by bmiller

1 replies • 13491 views

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