Mixed-Signal Design

Latest Posts

Discussion

pss simulation issues

Category: Mixed-Signal Design

By Binhngo1210
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updated over 3 years ago by Binhngo1210

2 replies • 11134 views
Discussion

Netlist bus naming convention in ADE XL and VCD files

Category: Mixed-Signal Design

By nomart
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started over 3 years ago

0 replies • 10462 views
Discussion

Want to assign a variable for a "string parameter" of veriloga block

Category: Mixed-Signal Design

By fatcat1206
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updated over 4 years ago by sergeiGorbikov

4 replies • 6495 views
Discussion

Different results using AMS simulator vs. Spectre simulator

Category: Mixed-Signal Design

By Bjorn VB
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updated over 4 years ago by FormerMember

8 replies • 18529 views
Discussion

Problem with understanding the noise integration

Category: Mixed-Signal Design

By Phong Phan
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updated over 4 years ago by Phong Phan

2 replies • 12734 views
Discussion

question on dyn_mosv check

Category: Mixed-Signal Design

By RZAQA
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started over 4 years ago

0 replies • 9523 views
Discussion

PSS failure for a ring VCO

Category: Mixed-Signal Design

By subhadeepdatta
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updated over 4 years ago by FormerMember

4 replies • 13009 views
Discussion

Spice to Spectre conversion

Category: Mixed-Signal Design

By sram17
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updated over 4 years ago by sram17

17 replies • 18632 views
Discussion

Running Monte carlo simulations in Process corners(SS,FF..)

Category: Mixed-Signal Design

By Jayanta
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started over 4 years ago

0 replies • 1697 views
Discussion

Set initial value for inputs/outputs for verilog cells in mixed-signal simulation (XCELIUM UNL)

Category: Mixed-Signal Design

By patschouly
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updated over 4 years ago by patschouly

1 replies • 3922 views
Discussion

Verilog-A module instantiating

Category: Mixed-Signal Design

By Jacob Bao
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updated over 4 years ago by Andrew Beckett

5 replies • 22040 views
Discussion

Does xrun support connection module between nettype and logic?

Category: Mixed-Signal Design

By RZAQA
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updated over 4 years ago by Andrew Beckett

1 replies • 1943 views
Discussion

In Cadence simulation how to introduce noise in current source

Category: Mixed-Signal Design

By nisgup
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updated over 4 years ago by Andrew Beckett

9 replies • 19036 views
Discussion

Virtuoso: cloning vs unit cell

Category: Mixed-Signal Design

By AshutoshLayout
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updated over 4 years ago by Andrew Beckett

1 replies • 11246 views
Discussion

Problem with ahdlcmi module library

Category: Mixed-Signal Design

By ID90
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updated over 4 years ago by ID90

4 replies • 11993 views

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