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Mixed-Signal Design

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  • Discussion

    How to instantiate module ports by name when port bus defined individually - VerilogAMS

    Category: Mixed-Signal Design

    By SimhanAnalog

    •

    updated over 10 years ago by Andrew Beckett

    1 replies • 3978 views
  • Discussion

    DCO test using Verilog A "unexpected statement "{""

    Category: Mixed-Signal Design

    By Yizhe Hu

    •

    updated over 10 years ago by Andrew Beckett

    5 replies • 3693 views
  • Discussion

    ncsim with Ultrasim very slow for post layout simulation

    Category: Mixed-Signal Design

    By dogrush

    •

    updated over 10 years ago by dogrush

    2 replies • 15545 views
  • Discussion

    VHDL-AMS VIEW LIST in ADE

    Category: Mixed-Signal Design

    By eppo

    •

    updated over 10 years ago by Andrew Beckett

    3 replies • 17120 views
  • Discussion

    Netlist should have explicit net definitions AMS

    Category: Mixed-Signal Design

    By SimhanAnalog

    •

    updated over 10 years ago by SimhanAnalog

    6 replies • 19122 views
  • Discussion

    too few terminals given

    Category: Mixed-Signal Design

    By Karev11

    •

    updated over 10 years ago by Andrew Beckett

    1 replies • 17948 views
  • Discussion

    nestlister error when using AMSD

    Category: Mixed-Signal Design

    By dogrush

    •

    updated over 10 years ago by Andrew Beckett

    3 replies • 17268 views
  • Discussion

    Cannot use input vector as stimuli when performing AMS simulation with irun.

    Category: Mixed-Signal Design

    By dogrush

    •

    updated over 10 years ago by dogrush

    2 replies • 16775 views
  • Discussion

    ncelab: *N,DLWTLK

    Category: Mixed-Signal Design

    By nikiva

    •

    started over 10 years ago

    0 replies • 1483 views
  • Discussion

    AMS-Sim

    Category: Mixed-Signal Design

    By MARON

    •

    updated over 10 years ago by Andrew Beckett

    1 replies • 14960 views
  • Discussion

    how to interrupt layout refresh in ic5141

    Category: Mixed-Signal Design

    By Karev11

    •

    updated over 10 years ago by Karev11

    4 replies • 15782 views
  • Discussion

    [SOLVED] unable to compile with genvar variable in veriloga

    Category: Mixed-Signal Design

    By msharma

    •

    updated over 10 years ago by msharma

    2 replies • 22837 views
  • Discussion

    SystemVerilog import into DFII

    Category: Mixed-Signal Design

    By Cotomaznamenat

    •

    updated over 10 years ago by Cotomaznamenat

    2 replies • 17699 views
  • Discussion

    Import a non-linear electro-thermal reduced-order model in SPECTRE ?

    Category: Mixed-Signal Design

    By Herge

    •

    started over 10 years ago

    0 replies • 14368 views
  • Discussion

    Regarding Cadence Virtuoso gpdk45nm technology spectre model file.

    Category: Mixed-Signal Design

    By PS90

    •

    started over 10 years ago

    0 replies • 14534 views
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