• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Cadence Online Support

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      DavidJHutchins
      DavidJHutchins 110 Points
    • 2
      excellon1
      excellon1 90 Points
    • 3
      OO202504185631
      OO202504185631 50 Points
    • 3
      AM202508216721
      AM202508216721 50 Points
    • 3
      AG202508246034
      AG202508246034 50 Points
  • Leaderboard

    • 1
      steve
      steve 17,554 Points
    • 2
      oldmouldy
      oldmouldy 13,545 Points
    • 3
      eDave
      eDave 10,166 Points
    • 4
      ShawnLogan
      ShawnLogan 9,660 Points
    • 5
      skillUser
      skillUser 7,617 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    Voltus-Fi-XL : generated path of mergedCurrents.rpt

    Category: Custom IC Design

    By SY202508201356 SY202508201356

    •

    started 21 days ago

    0 replies • 432 views
  • Discussion

    Pass variables to tcl script in Xcelium

    Category: Functional Verification

    By JF202503209845 JF202503209845

    •

    updated 21 days ago by StephenH

    1 replies • 1910 views
  • Discussion

    SimVision: how to find all signals in the database matching a specific pattern?

    Category: Functional Verification

    By ES20241003727 ES20241003727

    •

    updated 21 days ago by StephenH

    1 replies • 1787 views
  • Discussion

    Functional Coverage at SOC or Sub System Level

    Category: Functional Verification

    By TM202505254140 TM202505254140

    •

    updated 21 days ago by StephenH

    1 replies • 1141 views
  • Discussion

    vmanager: custom result evaluation

    Category: Functional Verification

    By ND202411057246 ND202411057246

    •

    updated 21 days ago by StephenH

    1 replies • 715 views
  • Discussion

    Can I change *.ucd type of file into .json to add svseed, coverpoints

    Category: Functional Verification

    By SV202408068842 SV202408068842

    •

    updated 21 days ago by StephenH

    1 replies • 599 views
  • Discussion

    Want to run Vmanager in batch mode

    Category: Functional Verification

    By PB20250805136 PB20250805136

    •

    updated 21 days ago by StephenH

    1 replies • 532 views
  • Discussion

    Exclusion of Signals Across Hierarchy for Toggle Coverage using CCF File

    Category: Functional Verification

    By WA20250805177 WA20250805177

    •

    updated 21 days ago by StephenH

    1 replies • 394 views
  • Answered

    datatip information

    Category: Allegro X PCB Editor

    By masamasa masamasa

    •

    updated 21 days ago by masamasa

    7 replies • 1027 views
  • Not Answered

    Our anti-virus just flagged \Cadence\SPB_24.1\tools\bin\repln.exe

    Category: Login, Licensing & Installation

    By MS202503286724 MS202503286724

    •

    updated 21 days ago by ILSTeamMember

    1 replies • 180 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information