• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      Charlie
      Charlie 110 Points
    • 2
      Aurel B
      Aurel B 74 Points
    • 3
      AC20250829806
      AC20250829806 60 Points
    • 4
      oldmouldy
      oldmouldy 55 Points
    • 5
      Hoangkhoipcb
      Hoangkhoipcb 50 Points
  • Leaderboard

    • 1
      steve
      steve 17,729 Points
    • 2
      oldmouldy
      oldmouldy 13,685 Points
    • 3
      eDave
      eDave 10,301 Points
    • 4
      ShawnLogan
      ShawnLogan 9,700 Points
    • 5
      skillUser
      skillUser 7,498 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    How to speed up PSpice Simulation Runs?

    Category: PSpice

    By AyushD

    •

    started over 1 year ago

    0 replies • 3329 views
  • Discussion

    Updating Modules in Layout with Pulse Module Manager

    Category: Allegro X Pulse & EDM

    By DesignTech

    •

    started over 1 year ago

    0 replies • 1313 views
  • Discussion

    Snap grid setup

    Category: Custom IC Design

    By ManjunathYalameli

    •

    updated over 1 year ago by Andrew Beckett

    2 replies • 4769 views
  • Discussion

    new simulation kills the previous running one

    Category: Custom IC Design

    By Svilen64

    •

    updated over 1 year ago by Svilen64

    3 replies • 4703 views
  • Discussion

    Changing the number of stdVia arrays with different sizes of vias in a limited area

    Category: Custom IC SKILL

    By dakuang01

    •

    updated over 1 year ago by dakuang01

    3 replies • 4466 views
  • Suggested Answer

    another fillet question

    Category: Allegro X PCB Editor

    By masamasa

    •

    updated over 1 year ago by John T

    7 replies • 5990 views
  • Discussion

    RF Link Budget Calculation Guide

    Category: AWR Design Environment

    By OscPn

    •

    started over 1 year ago

    0 replies • 2433 views
  • Suggested Answer

    Older OrCAD schematic viewing. translation error STD.CFG file

    Category: Allegro X Capture CIS

    By Seaward Lampray

    •

    updated over 1 year ago by Akshay khosla

    1 replies • 2594 views
  • Discussion

    Delete layer through hierarchy

    Category: Custom IC Design

    By Duc Loc

    •

    updated over 1 year ago by RobMan

    1 replies • 3771 views
  • Discussion

    How to run Celsius Thermal Solver in AWR

    Category: AWR Design Environment

    By SimTech

    •

    updated over 1 year ago by OscPn

    2 replies • 3120 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information