• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      KS202606109251
      KS202606109251 85 Points
    • 2
      AC202503109020
      AC202503109020 70 Points
    • 3
      HP20260601263
      HP20260601263 50 Points
    • 4
      FK202606088435
      FK202606088435 42 Points
    • 5
      RM202605273230
      RM202605273230 35 Points
  • Leaderboard

    • 1
      steve
      steve 17,869 Points
    • 2
      oldmouldy
      oldmouldy 13,830 Points
    • 3
      eDave
      eDave 10,381 Points
    • 4
      ShawnLogan
      ShawnLogan 9,725 Points
    • 5
      skillUser
      skillUser 7,518 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    How to change an attribute of a component group using console commands in Allegro Design Entry HDL

    Category: PCB Design

    By Daniel Tormo

    •

    updated over 7 years ago by Daniel Tormo

    1 replies • 17023 views
  • Discussion

    pass arrayed variable from ocean to design

    Category: Custom IC SKILL

    By DavidLou

    •

    updated over 7 years ago by DavidLou

    2 replies • 15614 views
  • Discussion

    Remove design variable "(name=value)" pairs in ViVA waveform names

    Category: Custom IC Design

    By MatthewLove

    •

    updated over 7 years ago by MatthewLove

    6 replies • 3654 views
  • Discussion

    stop layout snapping two close by cells to overlap

    Category: Custom IC Design

    By DavidLou

    •

    updated over 7 years ago by DavidLou

    4 replies • 18913 views
  • Discussion

    Library Path display issue

    Category: Custom IC Design

    By wenckey

    •

    updated over 7 years ago by Andrew Beckett

    7 replies • 19861 views
  • Discussion

    editing icadv layout data in 6.1.x virtuoso

    Category: Custom IC SKILL

    By gg111

    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 15219 views
  • Discussion

    Fastest way to merge two lists without duplicates

    Category: Custom IC SKILL

    By zmleitao

    •

    updated over 7 years ago by Dushyant

    9 replies • 22471 views
  • Discussion

    What does area reported by RTL compiler mean?

    Category: Logic Design

    By rexnyu

    •

    updated over 7 years ago by Andrew Beckett

    6 replies • 37497 views
  • Discussion

    wrapper for existing PCELL

    Category: Custom IC SKILL

    By ajni

    •

    updated over 7 years ago by Andrew Beckett

    1 replies • 15167 views
  • Discussion

    Bind key for setting to "copy reference" mode in the "Quick Align" window.

    Category: Custom IC Design

    By Arokia

    •

    updated over 7 years ago by Arokia

    7 replies • 6650 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information