• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      JCTEYSSIER0
      JCTEYSSIER0 85 Points
    • 2
      oldmouldy
      oldmouldy 65 Points
    • 2
      ltoohey
      ltoohey 65 Points
    • 4
      Hoangkhoipcb
      Hoangkhoipcb 50 Points
    • 4
      MD202602226914
      MD202602226914 50 Points
  • Leaderboard

    • 1
      steve
      steve 17,774 Points
    • 2
      oldmouldy
      oldmouldy 13,770 Points
    • 3
      eDave
      eDave 10,331 Points
    • 4
      ShawnLogan
      ShawnLogan 9,720 Points
    • 5
      skillUser
      skillUser 7,518 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    ncvlog: *E,WKLNDF error

    Category: Functional Verification

    By TAZZMANIAN

    •

    started over 8 years ago

    0 replies • 1518 views
  • Discussion

    Determine Cellview used in Test using SKILL in ADE-XL

    Category: Custom IC SKILL

    By KGh94

    •

    updated over 8 years ago by KGh94

    4 replies • 15440 views
  • Discussion

    Performing Mixed-Signal Simulation (Postlayout + Verilog-Functional)

    Category: Mixed-Signal Design

    By dpalomeq

    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 15114 views
  • Discussion

    find long nest on layout

    Category: Custom IC SKILL

    By mlea

    •

    updated over 8 years ago by Andrew Beckett

    4 replies • 14778 views
  • Discussion

    Creating a Mitred Microstrip 45 degree bend in Cadence Allegro without using the Analog RF Option

    Category: Allegro X PCB Editor

    By craigswanson

    •

    started over 8 years ago

    0 replies • 15411 views
  • Discussion

    PSTB loop-gain Phase-plot : error at lower frequency

    Category: Custom IC Design

    By jdp721

    •

    updated over 8 years ago by jdp721

    4 replies • 18169 views
  • Discussion

    17.20 Importing .MAX into Allegro ?

    Category: PCB Design

    By UlfK

    •

    updated over 8 years ago by Dale Peterson

    3 replies • 14516 views
  • Discussion

    How to get the preprocessor output from irun?

    Category: Functional Verification

    By Jeff000

    •

    updated over 8 years ago by StephenH

    7 replies • 6406 views
  • Discussion

    NCSIM problem during functional simulation with Vivado

    Category: Functional Verification

    By anjo

    •

    started over 8 years ago

    0 replies • 14075 views
  • Discussion

    How to compare what Spectre interprets from the raw s-parameter file?

    Category: RF Design

    By bobtest

    •

    updated over 8 years ago by Tawna

    4 replies • 20824 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information