• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      BB202608098129
      BB202608098129 80 Points
    • 2
      Zhifeng Jin
      Zhifeng Jin 75 Points
    • 3
      oAwad
      oAwad 40 Points
    • 4
      Hoangkhoipcb
      Hoangkhoipcb 31 Points
    • 5
      steve
      steve 30 Points
  • Leaderboard

    • 1
      steve
      steve 17,909 Points
    • 2
      oldmouldy
      oldmouldy 13,845 Points
    • 3
      eDave
      eDave 10,386 Points
    • 4
      ShawnLogan
      ShawnLogan 9,725 Points
    • 5
      skillUser
      skillUser 7,518 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    Tracing a net connection from M1 to the top most metal in layout using SKILL script

    Category: Custom IC SKILL

    By MSP032

    •

    updated over 1 year ago by MSP032

    7 replies • 7310 views
  • Discussion

    how to set stop list for a hierarchical instance by using cphSetInstStopList ?

    Category: Custom IC SKILL

    By DaveZhang

    •

    started over 1 year ago

    0 replies • 4020 views
  • Not Answered

    How to resolve this error while adding element in AWR?

    Category: AWR Design Environment

    By NP202408116448

    •

    updated over 1 year ago by OscPn

    1 replies • 2830 views
  • Discussion

    Load Pull transistor simulation

    Category: RF Design

    By Azaro

    •

    updated over 1 year ago by Azaro

    4 replies • 10064 views
  • Discussion

    control size of hiDisplayProgressBox

    Category: Custom IC SKILL

    By psill00

    •

    updated over 1 year ago by Andrew Beckett

    3 replies • 4837 views
  • Discussion

    Why my Verilog‘s digital outputs are correct in Vivado but 'x' in Cadence AMS?

    Category: Mixed-Signal Design

    By Cookies

    •

    updated over 1 year ago by Cookies

    4 replies • 3342 views
  • Not Answered

    Load Pull - Power delivered to the load

    Category: AWR Design Environment

    By Azaro

    •

    updated over 1 year ago by CurtisAWR

    1 replies • 1490 views
  • Discussion

    Getting error while adding element in AWR software

    Category: RF Design

    By NP202408116448

    •

    updated over 1 year ago by CurtisAWR

    1 replies • 6379 views
  • Suggested Answer

    How can I improve cross probing in PCB Designer and Capture

    Category: Allegro X Capture CIS

    By PeteV

    •

    updated over 1 year ago by Siliconmaster

    4 replies • 9668 views
  • Discussion

    copy the layout from one block to another block

    Category: Custom IC Design

    By rtyuy

    •

    started over 1 year ago

    0 replies • 4272 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information