• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      Charlie
      Charlie 110 Points
    • 2
      eDave
      eDave 70 Points
    • 3
      AC20250829806
      AC20250829806 60 Points
    • 4
      oldmouldy
      oldmouldy 45 Points
    • 5
      ShawnLogan
      ShawnLogan 40 Points
  • Leaderboard

    • 1
      steve
      steve 17,729 Points
    • 2
      oldmouldy
      oldmouldy 13,685 Points
    • 3
      eDave
      eDave 10,331 Points
    • 4
      ShawnLogan
      ShawnLogan 9,700 Points
    • 5
      skillUser
      skillUser 7,498 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    Modify the existing Board file data

    Category: Allegro X PCB Editor

    By Chinnu123

    •

    started over 15 years ago

    0 replies • 12977 views
  • Discussion

    export pinlist to text file

    Category: Allegro X PCB Editor

    By Chinnu123

    •

    updated over 15 years ago by Ejlersen

    3 replies • 15139 views
  • Discussion

    Off-Grid pins warning in abstract generation

    Category: Custom IC Design

    By affaq

    •

    updated over 15 years ago by Alex Soyer

    3 replies • 14786 views
  • Discussion

    example how to use the axlairgap command

    Category: Allegro X PCB Editor

    By Queen10

    •

    updated over 15 years ago by Queen10

    2 replies • 13999 views
  • Discussion

    subciruit initiated top-level current probe

    Category: Custom IC Design

    By Kalimero

    •

    updated over 15 years ago by Kalimero

    5 replies • 17546 views
  • Discussion

    How to void shape for same net Bond Finger in APD16.2

    Category: Allegro X APD

    By Alice 2009

    •

    updated over 15 years ago by Alice 2009

    2 replies • 14089 views
  • Discussion

    How To Close a Polygon

    Category: Allegro X PCB Editor

    By raniv

    •

    updated over 15 years ago by raniv

    3 replies • 14257 views
  • Discussion

    cadence verilog ams environment setup question

    Category: Custom IC Design

    By Wing2

    •

    updated over 15 years ago by EricCDN

    1 replies • 19300 views
  • Discussion

    Shape option in Via Structure

    Category: Allegro X APD

    By package design

    •

    updated over 15 years ago by mikem

    1 replies • 13583 views
  • Discussion

    Importing vias in Allegro APD

    Category: Allegro X APD

    By Siraj Akhtar

    •

    updated over 15 years ago by mikem

    3 replies • 16374 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information