• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      excellon1
      excellon1 157 Points
    • 2
      masamasa
      masamasa 139 Points
    • 3
      steve
      steve 100 Points
    • 3
      DavidJHutchins
      DavidJHutchins 100 Points
    • 5
      DG202504226528
      DG202504226528 91 Points
  • Leaderboard

    • 1
      steve
      steve 17,699 Points
    • 2
      oldmouldy
      oldmouldy 13,625 Points
    • 3
      eDave
      eDave 10,251 Points
    • 4
      ShawnLogan
      ShawnLogan 9,660 Points
    • 5
      skillUser
      skillUser 7,617 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    *** CRASHED *** [signal 11] Segmentation fault (core dumped) invoking tempus

    Category: Digital Implementation

    By Neubee

    •

    started over 2 years ago

    0 replies • 6016 views
  • Discussion

    Trigger callbacks when changing the cdf parameters of an instance

    Category: Custom IC SKILL

    By lordosGouv

    •

    updated over 2 years ago by skillUser

    1 replies • 6497 views
  • Discussion

    Most Talked About Topics in PSpice: We've Got You Covered!

    Category: PSpice

    By DesignTech

    •

    updated over 2 years ago by DesignTech

    3 replies • 1525 views
  • Not Answered

    Modifying an Existing BRD file to a bigger outline Software won't let me maintain Copper Pours

    Category: Allegro X PCB Editor

    By Neil mustafa

    •

    updated over 2 years ago by Schulz Jordan

    5 replies • 1693 views
  • Discussion

    General window name/ID for Layout and Schematic Windows to use "hiResizeWindow" function?

    Category: Custom IC SKILL

    By Lyrical

    •

    updated over 2 years ago by Lyrical

    4 replies • 3334 views
  • Discussion

    How to constrain actual via current as per IPC-2221A specification in PowerDC

    Category: Sigrity

    By SimTech

    •

    updated over 2 years ago by SimTech

    1 replies • 6058 views
  • Not Answered

    How to Rename Netgroup

    Category: Allegro X Capture CIS

    By SimpleFix

    •

    updated over 2 years ago by SimpleFix

    2 replies • 5326 views
  • Discussion

    process corner simulation

    Category: Custom IC Design

    By liangqunshan

    •

    updated over 2 years ago by liangqunshan

    2 replies • 7117 views
  • Suggested Answer

    How do you search these posts?

    Category: Allegro X PCB Editor

    By tshinseki

    •

    updated over 2 years ago by mahimag

    3 replies • 7472 views
  • Not Answered

    Bug: The NetGroup Block lose main Pin

    Category: Allegro X Capture CIS

    By daivermaster

    •

    updated over 2 years ago by rg13

    1 replies • 4161 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information