• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      DavidJHutchins
      DavidJHutchins 200 Points
    • 2
      Aurel B
      Aurel B 107 Points
    • 3
      bdc66a938f164d
      bdc66a938f164d 98 Points
    • 4
      excellon1
      excellon1 86 Points
    • 5
      oldmouldy
      oldmouldy 80 Points
  • Leaderboard

    • 1
      steve
      steve 17,599 Points
    • 2
      oldmouldy
      oldmouldy 13,625 Points
    • 3
      eDave
      eDave 10,206 Points
    • 4
      ShawnLogan
      ShawnLogan 9,660 Points
    • 5
      skillUser
      skillUser 7,617 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Suggested Answer

    How to prevent flooding under components?

    Category: Allegro X PCB Editor

    By Manfred1

    •

    updated over 3 years ago by Annette Fleming

    6 replies • 10319 views
  • Not Answered

    error in startup script

    Category: Allegro X PCB Editor

    By myil17

    •

    updated over 3 years ago by Dallas Steele

    3 replies • 8986 views
  • Discussion

    In the Assembler corner UI: Can we make one corner variable dependent on another variable?

    Category: Custom IC Design

    By StephanWeber

    •

    updated over 3 years ago by FormerMember

    3 replies • 8395 views
  • Discussion

    Problem with calibre RVE Highlights

    Category: Custom IC Design

    By RicardoGV1

    •

    updated over 3 years ago by RicardoGV1

    5 replies • 12172 views
  • Discussion

    Having trouble finding an object in a Capture Design?

    Category: Allegro X Capture CIS

    By DesignTech

    •

    started over 3 years ago

    0 replies • 6590 views
  • Not Answered

    How to modify all the packages in my library easily ?

    Category: Allegro X PCB Editor

    By DBTCH

    •

    updated over 3 years ago by chrishen

    3 replies • 8704 views
  • Discussion

    Cadence liberate: Different vdd value for backgate

    Category: Custom IC Design

    By NKFET

    •

    started over 3 years ago

    0 replies • 7249 views
  • Discussion

    Can I preset the width and length of simulator log file viewer?

    Category: Custom IC Design

    By StephanWeber

    •

    updated over 3 years ago by StephanWeber

    5 replies • 8649 views
  • Discussion

    python code to compare 2 LEF

    Category: Custom IC Design

    By san2696

    •

    updated over 3 years ago by san2696

    2 replies • 8448 views
  • Discussion

    valid vias skipped in viaSetDefaultValidViaDefs setting

    Category: Custom IC SKILL

    By dfink

    •

    updated over 3 years ago by Andrew Beckett

    5 replies • 9052 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information