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Forum - Thread List
  • Discussion

    How to remove highlight after DRC check in IC Layout design Locked

    14603 views
    5 replies
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    Reporting non-RC gated flops Locked

    16825 views
    2 replies
    Latest over 4 years ago
    by Max Bjurling
  • Discussion

    Getting the wellpin in lef using abstract Locked

    11141 views
    1 reply
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    Abrupt closing in OrCAD PCB

    11286 views
    2 replies
    Latest over 4 years ago
    by marekmat
  • Discussion

    preparation for verifying large blocks Locked

    13764 views
    8 replies
    Latest over 4 years ago
    by FormerMember
  • Not Answered

    OrCAD Capture hierarchical block import / export 0

    11073 views
    2 replies
    Latest over 4 years ago
    by ichliebedich
  • Discussion

    Trace a net backwards Locked

    15681 views
    7 replies
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    Shows Unrouted net but no route is there

    11306 views
    2 replies
    Latest over 4 years ago
    by Sugreev
  • Discussion

    Error - Shape to SMD Pin spacing

    6421 views
    9 replies
    Latest over 4 years ago
    by Sugreev
  • Not Answered

    Capture - Net name from port name 0

    5319 views
    3 replies
    Latest over 4 years ago
    by steve
  • Discussion

    How to close design in Innovus or remove design from Innovus (remains on disk)? Locked

    21916 views
    1 reply
    Latest over 4 years ago
    by Dimo M
  • Discussion

    Genus - Hierarchy Locked

    8273 views
    1 reply
    Latest over 4 years ago
    by Dimo M
  • Discussion

    passing variable number of params in spectre subckt call? Locked

    12225 views
    1 reply
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    Cadence Abstract DLNOLK : Failed to get exclusive lock Locked

    12249 views
    1 reply
    Latest over 4 years ago
    by Andrew Beckett
  • Discussion

    VHDL IEEE Library not recognized by RTL Compiler or Genus Locked

    16089 views
    1 reply
    Latest over 4 years ago
    by Dimo M
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