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"Omnia Gallia in tres partes divisa est" were the opening words to Julius Caesar's account of the Gallic war. All Gaul is divided into three parts. He went on to explain that they were the Belgians in the north east, the Aquitaine south of the Loire river...

In this week's Whiteboard Wednesdays video, Paul Garden provides more details on the new Tensilica Fusion G3 DSP features. He’ll discuss the benefits of the 128-bit SIMD ALU, instruction formats, auto-vectorizing compiler, and the software DSP library. The Fusion G3 is a fixed- and floating-point DSP for automotive, mobile, industrial, and general embedded DSP applications, is easy to program, and has exceptional out…

This month we released 10 new Verification IP for leading-edge protocols! Did I say 10? Yet again, we continue to be first in the market with support for protocols used in leading-edge applications like video-on-demand, cloud computing, big data, and higher resolution videos that are used in the automotive, mobile, enterprise networking, and consumer industries.

What are those 10 protocols that will help you design…

Today we have UVM, the universal verification methodology. This is great for verifying IP blocks. But when it comes to verifying at the system level, something higher level is required, something that allows verification to move up to the system level...

The big buzz in the automotive industry lately is autonomous driving vehicles. Companies like Mercedes, BMW, Google, and Tesla have already released, or are soon to release, self-driving features that give the car some ability to drive itself. Several other companies are also currently working on this technology. As a result, future cars will be equipped with sensor clusters, more computing power, Car2X communication…

It's verification week this week, with 5 posts about various aspects of Cadence's portfolio of verification tools.

http://youtu.be/1xOgXlm8bc0

Monday: At CDNLive in Bengaluru, Michal Siwiński gave a Verification Technology Update. Learn about...

At CDNLive in Bengaluru last week, Michal Siwiński gave a technology update on verification to everyone. Well, the PCB folks had already gone off to another room for their own update. The first thing that he pointed out is that verification is starting...

At the Linley Mobile Conference recently, the morning after Linley's keynote was focused on 5G. It is easy to say that nobody knows what the next generation of mobile actually is, but it will be called 5G. The standardization process has been going on...

The MIPI DSI specification has come a long way from the days of its early introduction targeting mainly mobile applications to today, where it is finding use in very different industries like automotive and IoT. This evolution has been further expedited due to the introduction of the C-PHY.

The Display Serial Interface (DSI) is a specification by the Mobile Industry Processor Interface (MIPI) Alliance, which was aimed at…

CDNLive Bengaluru takes place over two days. But it is organized very differently from the two-day CDNLive Silicon Valley. The first day is dedicated to verification, the second day to implementation, both digital and custom/analog. As a result most people...

As I did at the Design Automation Conference in Austin earlier this year, I will put a blog out with the highlights of the day (at least the ones I saw, I can't attend every track obviously). It's not as good as being here, and it also serves as a trailer...

I've not been to Bengaluru for about 20 years, when I ran engineering at Compass and we were considering setting up an engineering group in India. I came out with an Indian business development guy and we looked at potential sites in Bangalore (as Bengaluru...

• Istvan Novak – Senior Principal Engineer at Oracle
• Kevin Roselle – Senior Staff Engineer at Qualcomm
• Stephen Scearce – Senior Manager of High Speed Design at Cisco
• Dale Becker – Chief Electronics Packaging Engineer at IBM
• Ken Willis – Product Engineering Director of High-Speed Analysis Products at Cadence

East Coast engineers won’t have to travel…

The 16.6-2015 Allegro PCB Editor release introduces a few new features that provide a persistent capability.

Read on for more details.


Persistent Snap Overview
As an update to the previously added Snap feature, Allegro PCB Editor now features improvements on the popular feature by including Persistent Snap functionality. Users who wish to maintain a specified snap and/or selection type throughout an Allegro session can…

This is the first weekly video "What's for Breakfast?" that previews the blog entries coming up the following week on Breakfast Bytes.

https://youtu.be/k6soQQyx-xE

Monday: RISC-V and Chisel. RISC-V is an important new instruction set...

Cadence was shut down for the week of July 4th, so I went to Japan with a friend who had never been before. Despite having been two or three dozen times before in my life, this was actually my first time in Japan as a tourist. I've had the occasional...

At the recent GSA Silicon Summit at the Computer History Museum in Mountain View, CA, the keynote was given by Wally Rhines on consolidation in the semiconductor industry, titled "Merger Mania." He started off by pointing out that the number of recent...

Chipworks buys hundreds of devices every year and strips them down to look at the silicon that is in them. In some cases, they go much further, decap the chips, and work their way down the layers so that they know which process it is in, how many tracks...

In this week's Whiteboard Wednesdays video, Chris Rowen describes how to use processor clusters to implement neural networks. This approach allows you to achieve higher frame rates, which leads to increased accuracy while processing large amounts of data and accurately analyzing the results.

www.youtube.com/watch

Flash memory is being utilized in computers and electronic devices found in Automotive, IoT, Drones, Connected Home, and other emerging applications, demanding ever higher transfer rates and lower latency. Expanding the flash Serial Peripheral Interface (SPI) accesses to 8 I/Os (hence Octal SPI) increases the Serial NOR Flash throughput and provide a more efficient solution for emerging applications, while providing backwards…

If you design with flash memory components or IP solutions, head on over to the Santa Clara Convention Center to attend the Flash Memory Summit that is being held August 9-11 in Santa Clara, California.

Cadence recently announced a partnership with Micron to support Micron’s high-performance, low pin count XTRMFlash interface as part of its controller IP portfolio. This new and faster NOR flash is going to revolutionize…

Last week was the Linley Mobile Conference, although it is now the Mobile and Wearables Conference. As always, Linley Gwenap gave the opening keynote with his overview of the industry. One milestone that coincidentally was announced is that Tim Cook,...

Scaled-sigma sampling (SSS) is an efficient algorithm to solve the high-yield estimation problem, which happens when your circuit needs to have a really low failure rate, like one in a million or one in a billion. This can be because you are designing a highly repetitive circuit like a memory cell or flip-flop, or you are an automotive or medical designer who just wants to be very…

The new Virtuoso ADE product suite is packaged with a lot of easy-to-use, productivity-enhancing, and robust features including a new set of SKILL functions that make it easy to write and deploy efficient regression scripts.The new functions can be used with both Virtuoso ADE Explorer and Virtuoso ADE Assembler, and provide ease and efficiency in setting up regression flows from batch mode. These functions can be used only…