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Breakfast Bytes: 2020 Is the Year of DDR5

Paul McLellan

I talked recently to Marc Greenberg, one of Cadence's experts on the memory market. Despite the fact that the JEDEC DDR5 standard is still under development, Marc says that: 2020 will be the year of DDR5. He is excited about it since a new DRA...
- 24 Mar 2020
Digital Design: Library Characterization Tidbits: Validating Libraries Effectively

Jommy

In this blog, I will brief you about two very useful Rapid Adoption Kits (RAKs) for Liberate LV Library Validation.
- 23 Mar 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Help with Electromagnetic Analysis - Part V

Kabir

Here is another blog in the multi-part series that aims at providing in-depth details of electromagnetic analysis in the Virtuoso RF solution. Read to learn about the nuances of port setup for electromagnetic analysis.
- 23 Mar 2020
Breakfast Bytes: Turing Award: Ed Catmull and Pat Hanrahan

Paul McLellan

Last week, the ACM announced this year's Turing Award would go to Pat Hanrahan and Ed Catmull for their work on computer graphics. The Turing Award is often colloquially regarded as the "Nobel Prize in Computer Science." It also c...
- 23 Mar 2020
Breakfast Bytes: Sunday Brunch Video for 22nd March 2020

Paul McLellan

https://youtu.be/b7ixzahr85s Made on my balcony (camera Carey Guo) Monday: Another Year of CadenceLIVE—with Updated Schedule Tuesday: Digital Full Flow for 5/7nm Wednesday: How Intel Manufactures Chips Thursday: RSA 2020: From Sulu to Penn &amp...
- 22 Mar 2020
Breakfast Bytes: Netflix and C...adence

Paul McLellan

Earlier in the week, I wrote about a couple of videos from Intel, about semiconductor manufacturing and the Intel Museum. But with the ongoing rebranding at Cadence, we have a few videos of our own. So when you're bored with your selection on Ne...
- 20 Mar 2020
Breakfast Bytes: RSA 2020: From Sulu to Penn & Teller

Paul McLellan

I attended the RSA Conference in San Francisco recently. I guess that is going to turn out to be the last conference that I attend for some time. All the other events in my plans have either been postponed or canceled. RSA is the name of a security ...
- 19 Mar 2020
System, PCB, & Package Design : IC Packagers: Design Element Label Management

Tyler

A few weeks ago, we talked about template text labels for design-specific information. There, we were focused on labels that are specific to the design as a whole: revision information, dates, authors, etc. Today, we’re looking at a diff...
- 18 Mar 2020
System, PCB, & Package Design : BoardSurfers: Creating Footprints Using Templates in Library Creator

Sanjiv Bhatia

With ECAD-MCAD Library Creator, you can easily create footprints for your parts using thousands of ready-to-use templates that are provided with the tool.
- 18 Mar 2020
Breakfast Bytes: How Intel Manufactures Chips

Paul McLellan

I happened to be looking for something on YouTube recently when I came across this video on Intel's YouTube channel. It's a bit cutesy at the beginning ("Hi, I'm Chip"), but in five minutes it gives a pretty good idea of how ch...
- 18 Mar 2020
定制IC芯片设计 : Virtuosity：回顾定制IC芯片设计博客的黄金时代

Dishika Majumdar

如果您错过了2019 发布的Virtuosity, Virtuoso Meets Maxwell 和Virtuoso Video Diary等博客专栏，或者您想了解已发布ISR中的增强功能，那么不要犹豫，请将此页面添加为书签，以获取相关信息。另外，更多新的内容，请随时关注后续博客！
- 17 Mar 2020
Analog/Custom Design: Virtuosity: Device Arrays in the Automated Device Placement and Routing Flow

Sravasti

Since the release of the Automated Device Placement and Routing solution last year, we have continued to improve and build upon it. In this blog, I’ll talk about the latest addition—the Auto Device Array form—how this is an integral piece of the new Automated Device Placement and Routing solution.
- 17 Mar 2020
System, PCB, & Package Design : New 3D Analysis Engine Offers Faster, More Accurate Simulations at Lower Cost

Sigrity

A multi-CPU architecture running on both cloud and on-premise computers can better optimize large 3D structures in ICs, packages, and PCBs serving high-speed signaling designs.
- 17 Mar 2020
Breakfast Bytes: Digital Full Flow for 5/7nm

Paul McLellan

One constant in the semiconductor and EDA industries is, of course, Moore's Law. Another is the continual need for improved accuracy and performance. Accuracy is needed to take account of the effects that we used to be able to ignore. Performan...
- 17 Mar 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Bumps, Bumps.... Where Are My Bumps?

Brian LaBorde

Bumps are central to the Virtuoso MultiTech Framework solution. Bumps provide a connection between stacked ICs, interposers, packages, and boards. Bump locations, connectivity, and other attributes are the basis for creating TILPs, which we combine to create system-level layouts.
- 16 Mar 2020
Breakfast Bytes: Another Year of CadenceLIVE—with Updated Schedule

Paul McLellan

It's not strictly true that it is another year of CadenceLIVE since we called the event CDNLive in the past. But it's time for my annual preview of the season of CadenceLIVE events around the world. It is primarily a conference for users of Cadence ...
- 16 Mar 2020
Verification: RAK Attack: Better Driver Tracing, Faster Palladium Build Time, UVM Register Map Automation

XTeam

Looking to learn? There's a bunch of new RAKs (Rapid Adoption Kits) available online now!

1) Indago 19.09 Better Driver Tracing and More

Are you new to Indago and not sure where to start? Luckily, there’s a new Rapid Adoption Kit for you: the Indago 19.09 Overview RAK! This neat package contains everything you need to get your debugging started through Indago. In four short labs, plus a brief introductory lab, you…
- 14 Mar 2020
Breakfast Bytes: Another Year, Another Book of Breakfast Bytes

Paul McLellan

There is a new edition of A Year of Breakfasts. How do you get a copy? You can get a free copy by attending any CadenceLIVE event this year. The picture below is a group of happy recipients of signed copies of last year's book when I was at CDN...
- 13 Mar 2020
The India Circuit: Is Every Day Really Women's Day? Yes And No.

Madhavi Rao

This week had a plethora of posts and articles on International Women's Day (IWD) that is celebrated on Mar 8. In fact, there are two blogs on the Cadence community page – one by Paul McLellan, and the other by Ashley Sneathen about the Cad...
- 12 Mar 2020
Breakfast Bytes: Breakfast Nibbles: Predictions for 2020...Plus How Did I Do in 2019?

Paul McLellan

Last year in my post Breakfast Nibbles: Predictions for 2019, I made various predictions for the year. Let's see how well I did. The predictions were also republished as the last chapter of last year's A Year of Breakfasts. 2019 Predictions ...
- 12 Mar 2020
System, PCB, & Package Design : BoardSurfers: Training Insights: Creating Custom Reports using ‘Extract’

Shreyansh

You must deal with many reports in your daily life – for your health, financial accounts, credit, your child’s academic records, and the count goes on. Ever noticed that these reports contain many details, most of which you don’t wa...
- 11 Mar 2020
Breakfast Bytes: Exponential Growth

Paul McLellan

In the semiconductor industry, we've been dealing with the exponential growth associated with Moore's Law for over 50 years. Even so, I don't think that gives us an intuitive understanding of exponential growth. Nobody seems to have a feeling about ...
- 11 Mar 2020
System, PCB, & Package Design : IC Packagers: The Different Types of Mirrors

Tyler

I’m not talking about carnival funhouse mirrors, but rather the different options for mirroring symbols, vias, and bond fingers in your IC Package layout. The Allegro Package Designer Plus and SiP Layout tools have two distinct styles of m...
- 10 Mar 2020
Breakfast Bytes: The Future's So Bright You've Gotta Wear Shades

Paul McLellan

The Cadence website looks different, doesn't it? We are obviously in the middle of a re-branding. This re-branding is driven by two things. One is just that it is good to refresh the look of the company from time to time so that it doesn't get dated....
- 10 Mar 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Common Goal for One Flow, Acquisitions Strengthen RF Flow

michaelthompson

Seven months ago, I pointed out the ongoing need for change, or revolution, in high-frequency design flows. Spreading design IP across multiple, unconnected tools, is leading to manufacturing and design errors. It also slows the design flow and forces designers to focus on keeping track of edits and updates and not on innovating. Keeping track of the right s-parameter file may be a necessary evil in your current design…
- 9 Mar 2020

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