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Breakfast Bytes: Maglev Trains

Paul McLellan

Earlier this week I was in Shanghai for CDNLive China. More about what was said there next week. Today's post is about getting to the hotel where CDNLive was held from the airport. Most people just take a taxi, but I like to try and use the local tr...
- 16 Aug 2019
Analog/Custom Design: Virtuosity: Automated Device Placement and Routing - Grid Generation

Sravasti

This blog, the third one in the Automated Device-Level Placement and Routing series, highlights the importance of following a gridded methodology for placement and routing. You'll see how the automated device-level layout flow lets you derive WSPs and row regions automatically, based on the device footprint, layers, and DRCs, with minimal user input.
- 15 Aug 2019
Breakfast Bytes: Black Hat: Glitching Microcontrollers

Paul McLellan

As a paid-up member of the semiconductor community, the most interesting presentation I saw at Black Hat was about glitching microcontrollers. One way that chips are vulnerable to security issues is that all our chip knowledge tells us that things ar...
- 15 Aug 2019
Breakfast Bytes: CDNLive Taiwan 2019

Paul McLellan

I haven't been to Taiwan since the last time I worked for Cadence in the early 2000s. At that time, I was running Custom IC, which also included physical verification—we were structured a bit differently back then. However, one reason behind th...
- 14 Aug 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - An Introduction to Palladium Cloud

References4U

In this week's Whiteboard Wednesdays video, Bennet Le provides an overview of the Cadence® Palladium® Cloud Solution and explains how virtually every company developing SoC designs can now take advantage of the extensive verification provided by the Palladium platform.

https://youtu.be/xLL6ynSm51o
- 13 Aug 2019
System, PCB, & Package Design : IC Packagers: Grouping Items with Symbol Instances

Tyler

Whether you’re adding lines, text, shapes, routing elements, or any other feature to the design, most elements assume that you are placing them at the design level. If they are part of the symbol, they would be part of the library object. Is there a quick and convenient way to take the additional elements and assign them to the placed symbols in your design so that everything stays together in easy to manipulate pieces…
- 13 Aug 2019
System, PCB, & Package Design : BoardSurfers: Five Ways to View Your Design in 3D Canvas

Monika

Five simple yet effective ways to increase efficiency by selecting the right objects you want to model, say, all the pins or a subset of the pins in a design.
- 13 Aug 2019
Breakfast Bytes: Black Hat: Phishing on Gmail

Paul McLellan

A few weeks ago I wrote a post Passwords and Multi-Factor Authentication about the scale of attacks on cloud providers and other services. At the recent Black Hat Security Conference in Las Vegas, Google's research lead for security, Elie Bu...
- 13 Aug 2019
Breakfast Bytes: Arm on Autonomous Automotive

Paul McLellan

Let me start this post with a brief history of autonomous driving. Most people date the start of the autonomous driving era to 2004, with the Grand Challenge in the Mojave Desert over a 150-mile course. That turned out to be 142 miles longer tha...
- 12 Aug 2019
Breakfast Bytes: Sunday Brunch Video for 11th August 2019

Paul McLellan

https://youtu.be/ZXa5ZZzAWXs Made at Cadence campus (camera Sean) Monday: Automotive Industry Basics Tuesday: Mary Meeker: How Much Is the Internet Growing? Wednesday: Mary Meeker: Fulfillment, News, and Money Thursday: Mary Meeker: Security, Gi...
- 11 Aug 2019
PCB、IC封装：设计与仿真分析: Ken的博客系列之一 | 多千兆串行接口的信号完整性方法

Sigrity

作者：Ken Willis 随着电子行业技术的发展，特别是在传输接口方面，从PCI到PCI Express、从ATA到SATA、从并行ADC接口到JESD204、从RIO到Serial RIO等等，无一都证明了传统并行接口的速度已经达到瓶颈，取而代之的是速度更快的串行接口，于是原本用于光纤通信的SerDes 技术成为了高速串行接口的主流。串行接口主要应用了差分信号传输技术，具有功耗低、抗干扰强，速度快的特点，诸如PCI Express®（PCIe®）Gen4等串行链路接口的数据传...
- 9 Aug 2019
Analog/Custom Design: Virtuoso Video Diary: Stimuli with Variable Sweeps Videos and Rapid Adoption Kit

Arja H

You're probably thinking, "wasn't there a recent blog on the new Stimuli Assignment form in ADE." Well yes, that's right, but we wanted to offer more functionality so from IC6.1.8 ISR4, we now have the ability to preview stimuli waveforms using swept variables. This will be really useful when defining your stimuli. There are a couple of other small usability changes too.
- 9 Aug 2019
Breakfast Bytes: AImotive: Shifting Gear in Automotive

Paul McLellan

At the recent Cadence Automotive Design Summit, Laszlo Kishonti, CEO of AImotive, presented From Walled Gardens to Collaboration: Shift in the Automated Driving Industry. AImotive is based in Budapest, and when introducing him, Cadence's Robert S...
- 9 Aug 2019
Breakfast Bytes: Mary Meeker: Security, Gigs, Healthcare, China

Paul McLellan

This is the third (of three) posts about Mary Meeker's 2019 report on Internet Trends. The first was on Monday. The second was yesterday. If you don't know who Mary Meeker is or what this report is, then start at the beginning....
- 8 Aug 2019
Breakfast Bytes: Mary Meeker: Fulfillment, News, and Money

Paul McLellan

This is the second post (of three) about Mary Meeker's 2019 report on Internet Trends. The first was yesterday. You should read that post first since this one simply picks up where that one left off. If you have no idea who Mary Meeker is, then y...
- 7 Aug 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Inductance Extraction for Digital Designs

References4U

In this week’s Whiteboard Wednesdays, Cadence expert Varun Raj Garapati explains how designers can address inductance effects on clocks, especially on digital SoCs. Using Quantus Extraction Solution for FinFET designs, designers can overcome reliability issues stemming from Inductance effects. To learn more visit https://www.cadence.com/go/quantus-extraction

www.youtube.com/watch
- 6 Aug 2019
System, PCB, & Package Design : IC Packagers: Six Steps of IC Packaging

mrigashira

Do you want to create an IC Package and are on the lookout for a tool that suits you? Or, you might already be using APD or SiP Layout but want to know their full potential. We will talk about six broad steps of IC Packaging and how APD and SiP Layout make the steps efficient and easy for you.
- 6 Aug 2019
System, PCB, & Package Design : BoardSurfers - Aerials and Bails: How to Rename Reference Designators Using Batch Command

Monika

Components on a board are often placed per their functional group and hence their reference designators are all jumbled up. It is a common practice to rename reference designators before sending out the design data to manufacturers. Reference designator...
- 6 Aug 2019
Breakfast Bytes: Mary Meeker: How Much Is the Internet Growing?

Paul McLellan

Every year Mary Meeker produces a big presentation on Internet Trends. And when I say big, I mean it. This year the presentation has 334 slides. In previous years, going back to 1995, Mary was a general partner at Kleiner Perkins, but she is now...
- 6 Aug 2019
Breakfast Bytes: Automotive Industry Basics

Paul McLellan

A couple of weeks ago Cadence held its second Automotive Design Summit here on the Cadence campus in San Jose. I will cover some of what was said over the next week or two, but I thought it might be good to do a recap on the basics of the automotive ...
- 5 Aug 2019
Breakfast Bytes: Sunday Brunch Video for 4th August 2019

Paul McLellan

https://youtu.be/5b0hczb-5FI Made at building 11 (camera Sean) Monday: Ludwigsburg: It's All About Return-on-Investment Tuesday: 5G in US vs Rest-of-World Wednesday: IEEE Unified Power Models Thursday: CHIPs: Interns around the World Friday:...
- 4 Aug 2019
Breakfast Bytes: My Boris Johnson Story

Paul McLellan

Boris Johnson is the new Prime Minister of Britain. Unlike most people who rise in politics, he has not been a career politician. Sure, he was Mayor of London from 2008 to 2016, beating the shoo-in Labor candidate and winning re-election to a se...
- 2 Aug 2019
Computational Fluid Dynamics: CREMHyG Analyzes Transient Flow in a Multi-Piston Pump Design

Veena Parthan

Author: Claude Rebattet, Head of CREMHyG laboratory, University of Grenoble Alpes, France The Grenoble Hydraulic Machinery Research and Testing Centre (CREMHyG) is a Grenoble Institute of Technology (Grenoble INP) laboratory. The turbomachinery te...
- 2 Aug 2019
PCB、IC封装：设计与仿真分析: Cadence Clarity为系统分析和设计提供前所未有的性能及容量

SDA China

本文转翻译自Cadence "Breakfast Bytes" 专栏作者Paul McLellan文章“Bringing Clarity to System Analysis”。 space 今年4月在Cadence用户大会——CDNLive硅谷站，Cadence公司CEO陈立武（Lip-Bu Tan）宣布了发布Cadence® Clarity 3D Solver。这是Cadence公司系统级分析策略下推出的第一款产品，突破性的电磁场（...
- 1 Aug 2019
System, PCB, & Package Design : 3D EM Simulation Is Necessary

Sigrity

Accurate 3D EM simulation is increasingly necessary as data rates increase. For example, last year Cadence announced IP for 112G long-reach SerDes. The IP lives on a 7nm chip, which is a reasonably well-controlled environment. But think what the sig...
- 1 Aug 2019

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