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In the previous couple of SKILL for the Skilled postings we looked at some of the features of SKILL++. In fact, we saw local functions, higher-order functions, and lexical scoping. In this episode of SKILL for the Skilled I would like to show a few more practical examples of these concepts.

Functions are first class

In the SKILL language, functions are themselves first class objects. They can be created dynamically…

Attendees of DesignCon 2011 received a sneak peek, and now Allegro PCB designers can officially check out a new power delivery network (PDN) analysis solution as part of the Allegro 16.5 release.  Accurate, flexible, and highly integrated, Allegro PCB Power Delivery Network Analysis provides a unique design and analysis solution.  With no translation of PCB designs required, users of either Allegro PCB SI or Allegro PCB…

Attendees of the Silicon Valley DVClub this past Tuesday were treated to some real life case studies of new tools that help D&V engineers rapidly create assertions (a full report on this event by Richard Goering is posted here) .  As it turns out, one of these case studies -- the presentation by Jing Lee of Broadcom on NextOp's BugScope tool -- had its origin in a poster session presented at DVCon 2011.  I had the…

After a long break, I'm going to try to venture back into the blogosphere, starting off nice and easy--by cheating...

You see, Virtuoso IC 6.1.5 came out at the end of January, and one of the changes made to the Schematic Editor is that many of the handy dockable assistants featured in IC 6.1 are now available at the basic L tier of software.  If you don't know what that means, don't worry, because what I'm trying to…

Allegro 16.5 is another step forward for Cadence towards the realization of the EDA360 vision. Part of that vision is System-on-Chip (SoC) Realization, and SoC Realization requires a broad-based, comprehensive solution for memory and storage IP. 

Because applications used on all types of handheld, desktop, and rack mounted platforms require faster access to data, memory interfaces are key elements for delivering on the…

In my last post, I described three different types of automatic assertions: those derived from the design, those derived from the design with some assumptions such as naming conventions, and those derived from the design plus supplemental files expressing some aspect of design intent. I finished by mentioning the approach taken by NextOp, which analyzes simulation traces to "learn" about a design's behavior…

Just in time for Easter, Team Verify's Apurva Kalia, Manu Chopra, and Suman Ray of the Incisive R&D team created a Rubik's Cube solving Lego robot.  However, unlike other such 'bots (recall the now famous ARM-driven Rubik's Cube ‘bot at ARM's TechCon), the brain of this one is actually a single SVA assertion that is solved in an instant by Incisive Formal Verifier (IFV).  Check it out:

If video…

The answer is "yes, you must initialize it" but the reason may be surprising to many people: DRAM contents are not lost when the power is turned…

There are a couple quick new SPB16.3 Allegro PCB Editor features to mention this week.

Flip Design

Viewing a layout from the bottom side is now available through the flipdesign (View — Flip Design) command or flip icon . The design is flipped about the Y axis.

A true bottom side view from a CAD system is essential when debugging a board in the lab or probing on the manufacturing floor. Design editing can also be done…

I have had a lot of discussions recently around improving the final integration of analog IP. There has been a lot of material published over the years to aid in this task, and I wanted to point to some of my favorites while talking about what has and has not changed.

There is a lot to be learned from digital verification methodologies applied to "big A" mixed signal designs, and the first is leveraging a systematic…

Mixed-signal verification has been one of the hottest topics in the past year, and it was very evident in DVCon 2011, looking at the number of technical papers submitted on this topic. Engineers are looking for solutions to solve tough problems in this space, and the creativity put into developing custom solutions is mind blowing. We are at an interesting stage where engineer's minds are racing past the capabilities of…

If you have defined relational fields in your Allegro Design Entry CIS configuration, you can now include the relation fields in your CIS Bill Materials. When you include relational data in your reports, you can also decide how you want this data displayed. So you can choose to display the relational data horizontally (in the same row) or vertically (one line item per related data).

A completely different perspective…

With the recent release of unified custom/analog flow that is based on the latest version of the Virtuoso IC 6.1.5 technologies (see Virtuoso IC 6.1.5 press release here), it is time to revisit the strengths of Virtuoso IC 6.1 platform and find out how new capabilities enable designers with the productivity gains they have been clamoring for.

Open Access and SKILL

One of the major changes in Virtuoso IC 6.1 is the database…

Videos on Enterprise Planner: What's it worth to you?

Submitted By MDV Team Member - Paul Carzola
Solutions Architect, Metric Driven Verification

If a picture is worth a thousand words, then a video must be priceless -- at least I hope you think so. Recently, we created a few improvised videos on how to get started with Enterprise Planner, the verification plan creation utility which is part of Incisive…

When two users report the same issue in the same week I'm glad I can share the problem and solution via this blog.

I know a lot of you work in an environment where you request computing resources via "bsub." In many cases it's frowned upon to request an xterm to launch jobs and it's preferred to start an interactive session with something like "bsub -I encounter." What we were seeing was that command line navigation…

As a complete gadget geek, it’s always exciting to play with the latest technological toys. But if you stop to consider how each new wave of applications powered by these devices impacts the underlying SoC designs, you quickly realize that the memory and storage subsystem is now central to SoC Realization. Poor memory and storage design will impact everything from the user experience to the applications that are possible…

Verifiers rejoice: today is the 1st anniversary of the launch of this blog!!!  To commemorate the occasion, allow us to highlight the top 5 posts (out of 25 total!) from the past year.  Without further adieu, in ascending order of web hits and comments received ...

#5 - "Everything Assertion Based" -- Assertion-Based Verification (ABV) Comes of Age for Complete Block-Level Verification
This post dares to claim that…

The UVM 1.0 release was the big story of DVCon 2011, as it's the first verification methodology officially supported by all three of the "Big 3" simulation vendors.  However, the very nature of the standard -- an open source library governed by a community similar in character to Linux itself -- also enables a whole host of vendors from pure-play IP companies to providers of best-of-breed productivity tools…

As regular readers know from previous posts, I have a lot of background in assertion-based verification (ABV) and how assertions are used in simulation and formal analysis. There has been a lot of growth in the use of both assertions and formal since I was first involved in these technologies in 1999, but it would be disingenuous of me to suggest that ABV is as mainstream as I hoped it would be by now. Assertion…

The ADW16.3 Allegro Design Workbench has a new Configuration Manager that simplifies installation and configuration of the ADW server and clients.

You can now report on the status of the server and it provides status on the following:

• Server version
• Memory allocation
• Log file location
• Database information

It allows you to easily create client installs for ADW and can be invoked as a batch script:

 

Read on for more details ……

While there was a lot (justifiable) buzz around the UVM 1.0 release, formal and assertion-based verification (ABV) technologies and methodologies also had a great showing at DVCon 2011.  Beyond the many papers and posters on this topic, further evidence of formal verification growth is the emergence of service providers that are exclusively focused on this category.  Specifically, Oski Technology -- "the world's first and…