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Latest Blog Posts

  • SoC and IP: Sign Up for Linley Mobile Conference – See Chris Rowen

    PaulaJones
    PaulaJones

    If you’ve never heard of the Linley Mobile Conference, you’ve been missing out on one of the most influential conferences for design innovation for next-generation mobile devices.

    Registration is now open for the Linley Mobile Conference, April 22-23, at the Hyatt Regency Hotel in Santa Clara, CA. And you’re going to want to attend.

    Just read the show’s description:

    Innovation in mobile chip…

    • 7 Apr 2015
  • Analog/Custom Design: Virtuosity: 19 Things I Learned in March 2015 by Browsing Cadence Online Support

    stacyw
    stacyw

    1. Cadence Online Support has a sleek new design along with support for iPAD and Android tablet (7" and above).   Find out what's new. (Note: Some users are experiencing display issues in Chrome version 41 and 42. Cadence is working to find a resolution. If you experience this, we suggest you use IE or Firefox until a fix for Chrome is identified.)

    Rapid Adoption Kits

    2. Design Rule Driven (DRD) Editing and DRD…

    • 6 Apr 2015
  • System, PCB, & Package Design : Power Integrity Solution Spans Multiple PCBs and Packages

    TeamAllegro
    TeamAllegro

    When designing next-generation products, the common theme is "faster, smaller, cheaper".  When that is combined with longer battery life and lower power consumption requirements, the design challenges can be daunting.  And one thing you know for sure, the project schedule is not going to be extended to allow you to overcome all these challenges.

    It certainly makes sense that every electronic product designer…

    • 3 Apr 2015
  • System, PCB, & Package Design : Customer Support Recommended—Design and Simulation of Full Bridge DC-DC SMPS Using AMS Simulator

    Naveen
    Naveen

    Switched Mode Power Supplies (SMPS) are used extensively in most of the power conversion processes due to their efficiency and compactness. The analysis, design, and the modeling processes have all grown in the past four decades. Most of these developments were centered on hard-switching converters where the switching frequency was limited to a few KHz. The present direction of evolution in SMPS is towards high efficiency…

    • 2 Apr 2015
  • Whiteboard Wednesdays: Whiteboard Wednesdays - LPDDR4 IP Verification Challenges

    References4U
    References4U

    In this week's Whiteboard Wednesdays video, YJ Patil discusses the challenges of LPDDR4 IP verification when designing high-speed, low-power memory for mobile SoCs.

    https://youtu.be/bPobqXqZq9M

    • 31 Mar 2015
  • SoC and IP: Call for Papers for MemCon Now Open

    PaulaJones
    PaulaJones

    What’s the biggest conference for everything related to memories? If you answered MemCon, you’d be right.

    MemCon 2015 is on Tuesday, October 13, 2015, at the Santa Clara Convention Center. The call for papers just opened, so it’s time to think about how you can further your career and showcase your understanding of key memory technologies.

    See the full list of suggested topics, but here are some of…

    • 30 Mar 2015
  • SoC and IP: Mobile World Congress: Enabling Systems with Sensor Fusion, DSPs

    Brian Fuller
    Brian Fuller

    BARCELONA, Spain—We hear a lot about sensor fusion and the applications that it can enable. But conquering the technical hurdles while keeping your project on budget is non-trivial.

    “What you’re going to see is that with a solid sensor fusion output, people are going to be building newer and better applications, like incorporating pedestrian dead reckoning with satellite GNSS information to get better tracking…

    • 30 Mar 2015
  • Digital Design: High-Level Synthesis: Why Now?

    dpursley
    dpursley
    March 27, 2015 – With a title like “Why Now?”, you might expect this to be a sales blog, a thinly veiled pitch trying to tell you why you should be using high-level synthesis (HLS) today. But, in fact, that is not the point at all. ...
    • 27 Mar 2015
  • Whiteboard Wednesdays: Whiteboard Wednesdays—The Power of WiGig (802.11ad)

    References4U
    References4U

    In this week's Whiteboard Wednesdays video, Bob Salem explains WiGig (IEEE 802.11ad), the next-generation wireless communication interface. Bob details how applications including entertainment, small office, small corporate groups, and hotspots all benefit from this powerful, wireless interface.

    https://youtu.be/eT1sT4Y_FjQ

    • 24 Mar 2015
  • System, PCB, & Package Design : What's Good About Allegro PCB Editor Highlight Nets Associated with Component? It’s in the 16.6 Release!

    Jerry GenPart
    Jerry GenPart

    With the 16.6 Allegro PCB Editor release, a simplified method to highlight or de-highlight all nets associated with a component is offered in all applications modes. Hover over a symbol(s), then use the RMB to access the ‘Highlight Associated Nets’ command. Nets assigned the DC Voltage property are ignored.

    Here are the steps to accomplish highlighting nets:

    1. Using any one of the application modes, hover…
    • 24 Mar 2015
  • SoC and IP: Link Training: Establishing Link Communication Between DisplayPort Source and Sink Devices

    Neelabh
    Neelabh

    Link training is the first stepping stone to enabling the communication channel between source and sink devices. This is where the electrical characteristics of the link along with the bitrate are fixed, and are subsequently used for the data transfers...

    • 23 Mar 2015
  • SoC and IP: ARM-Cadence IP Deal Propels Engineering Innovation Ahead: Martin Lund

    Brian Fuller
    Brian Fuller

    On March 18, Cadence and ARM announced a groundbreaking deal that provides reciprocal access to relevant IP portfolios from the Cadence IP Group and ARM. The agreement grants both companies rights to manufacture test chips containing Cadence IP and ARM IP and to provide development platforms to customers. I sat down with Martin Lund, Senior Vice President of Cadence’s IP Group, to talk about the deal.

    Q: What’s…

    • 18 Mar 2015
  • Whiteboard Wednesdays: Whiteboard Wednesdays—Cognitive Layering Technique for Low-Energy, Sensor-Rich Devices

    References4U
    References4U

    In this week's Whiteboard Wednesdays video, Chris Rowen talks about techniques for optimizing power in sensor-based IoT devices and always-on subsystems.

    https://youtu.be/GvyvZoH9RSY
    • 18 Mar 2015
  • SoC and IP: Mobile World Congress: Two New Audio IP Announcements

    Brian Fuller
    Brian Fuller

    BARCELONA, Spain—Mobile World Congress is not surprisingly focused on mobile devices, applications, and services. And the Cadence Tensilica team, which has been attending this event for a decade, generally has something up its sleeves when the booth opens for business each year.

    This time was no exception. The company announced that DTS’s Headphone:X immersive sound technology has been optimized for the Cadence…

    • 16 Mar 2015
  • Whiteboard Wednesdays: Whiteboard Wednesdays—Major Enhancements of the PCIe Gen 4 Specification

    References4U
    References4U

    In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan talks about the latest enhancements of PCI Express (PCIe) Gen 4 and how these enhancements address the goals of increased bandwidth while maintaining software compatibility and keeping power consumption and implementation costs down.

    http://youtu.be/Keh-utK5YKo

    • 10 Mar 2015
  • Life at Cadence: A Great Place to Do Great Work: Celebrating Our First Year on the FORTUNE List of the 100 Best Companies to Work For

    Tina Jones
    Tina Jones
    Innovation starts with our people. For over 25 years, Cadence has been a leader in the electronics revolution and continues to propel it forward. In an industry that requires constant creativity, collaboration, and deep technical knowledge, we consi...
    • 5 Mar 2015
  • SoC and IP: IP Requirements for Verifying CHI-Based Designs

    DimitryP
    DimitryP

    Just as IP components offload design effort, verification IP (VIP) components offload verification effort. VIP components are used to monitor traffic and substitute for selected master and slave components to enable controlled stimulus generation and coverage collection within an SoC design. To be effective in verifying CHI-based designs, the VIP must deliver three major capabilities. They are:

    1. Stimulus generation…
    • 4 Mar 2015
  • SoC and IP: Mobile World Congress: A Decade of Change in IP Innovation

    Brian Fuller
    Brian Fuller

    BARCELONA, Spain—In the past decade, immense change has come to mobile electronic system design. Steve Roddy should know. He’s had a ringside seat to those changes—and Mobile World Congress—for years.

    Roddy, senior group director for Tensilica marketing, said during MWC 2015 that system design is a much different challenge than it was a decade ago. (Tensilica, which Cadence acquired in 2013, has…

    • 4 Mar 2015
  • Analog/Custom Design: Virtuosity: 12 Things I Learned In February by Browsing Cadence Online Support

    stacyw
    stacyw
    Application Notes

    1. Voltus-Fi Power Analysis Support and Power Grid View Generation—Voltus-Fi to Voltus Flow

    The Voltus-Fi to Voltus flow provides the complete Cadence power integrity solution for full-chip power integrity analysis for all designs, featuring accurate transistor EMIR analysis and high-quality analog IP grid modeling. This application note covers the process of Voltus-Fi flow based on the 28nm…

    • 4 Mar 2015
  • SoC and IP: WiGig Has Arrived to Enable IoT Designs--and Cut the HDMI Cord!

    Steve Brown
    Steve Brown

    What is WiGig

    WiGig is the name given to a high-speed multi-gigabit wireless communications standard over unlicensed 60GHz radio frequency band established by the Wireless Gigabit Alliance in 2007. Since then it has become part of the WiFi Alliances and established as one of the IEEE 802.11ad protocol. As part of the WiFi Alliances, WiGig tri-band-enabled devices will operate in the 2.4, 5 and 60GHz radio band.

    WiGig…

    • 4 Mar 2015
  • Whiteboard Wednesdays: Whiteboard Wednesdays - Optimizing Power Via a Configurable Processor

    References4U
    References4U

    In this week’s Whiteboard Wednesdays, Chris Rowen takes a look at the basic energy equation for processors and how a configurable processor architecture provides the flexibility to optimize power for a given application. 

    http://youtu.be/gMrUIqovAIU

    • 3 Mar 2015
  • Analog/Custom Design: Virtuosity: 13 Things I Learned in January 2015 by Browsing Cadence Online Support

    stacyw
    stacyw

    'Tis the end of an era, folks. It should not be a surprise, but IC 5.1.41 reached End of Support as of 12/31/2014.

    1.  Where do I find the support lifecycle dates (e.g., End of Support) for Cadence releases?

    https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000051SLEAY&pageName=ArticleContent

    2.  Where do I find the product lifecycle letters?

    https://support.cadence.com/apex/ArticleAttachmentPortal…

    • 2 Mar 2015
  • System, PCB, & Package Design : What's Good About Allegro PCB Editor Find Filter Support of Hierarchical Constraint Objects? 16.6 Has It!

    Jerry GenPart
    Jerry GenPart

    The 16.6 Allegro PCB Editor release ‘Find by Name’ list now supports hierarchical database objects - Diff Pair, Match Group, Region, for example:

    16.5 Find by Name:

    16.6 Find by Name:

    Read on for more details …

    Invoke the ‘Assign Color’ command.

    Select ‘Diff Pair’ from the ‘Find by Name’ list.

    Click the ‘More’ button.

    Select a few Diff Pairs from…

    • 25 Feb 2015
  • Verification: Don’t Lose Extra Simulation Cycles

    teamspecman
    teamspecman

    After reading the rest of this blog, you might guess the truth, which is that my "designing" skills go back to the 8086 processor! In this blog, I have used a 64-bit register (Well, I could make it 16-bit, but…)  in the example, just to show that this issue is still relevant today.

    At any rate, the e verification issue that I describe here seems to be a common issue for many users.

    Assume that, in the…

    • 25 Feb 2015
  • Whiteboard Wednesdays: Whiteboard Wednesdays—Cadence VIP Ease of Use Project

    References4U
    References4U

    In this week's Whiteboard Wednesdays video, Herbert Rivera-Sanchez discusses the Cadence Verification IP (VIP) Ease of Use Project. This project addresses three main areas of concern: works out of the box, provides consistent integration and provides basic training to quickly bring customers to a productive level in a short time.

    http://youtu.be/fbsyfdPq4ho

    • 25 Feb 2015
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