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February was a big month for RAKs (Rapid Adoption Kits)!  If you haven't checked out the listings under Resources->Rapid Adoption Kits yet, you're missing out.  You'll find databases with detailed instructions, documentation and videos on many tools, features and flows.   They've become very popular and we're adding more all the time.

We're also featuring content on routing, schematic PCells, ADE XL…

When you write a define-as or define-as-computed e macro, you sometimes need the replacement code to contain or to depend on the source information regarding the specific macro call, including the source module and the source line number.

For example, a macro may need to print source information, or it may need to create different code when used in one module than it needs to create when used in other modules.

You can…

With another year of record attendance, DVCon has again proven that a functional verification-focused mix of trade show and technical conference is what customers need to get their jobs done.  Here are some of the some of the highlights I took away from this informative event:

DVCon 2013 was a one stop shop for panels, papers, posters,
live demos, and tutorials on functional verification

* Great panels on Verification Planning…

Implementing SoCs with embedded processors at advanced nodes has become increasingly difficult. This is due to the complexity of the design functionality as well as the low power and increased performance requirements driven by a plethora of end-user applications in modern hand-held devices. Path-breaking trends in ARMv8 64-bit processor based microservers for power efficient cloud computing/data centers and high-end…

The Allegro PCB Editor Place Replicate application now supports the processing of component reference designators. The work performed in customizing assembly text or silkscreen to the seed circuit can now be leveraged across the replicated modules.

Read on for more details…

In the image below there are two modules. The one on the left (U14, U15 and the associated capacitors) has the text moved to locations which…

The Allegro AMS Simulator (analog/mixed-signal) 16.6 release adds several enhancements to the Advanced Options dialog form. This enables the customizability of a PSpice simulation run, including control over convergence homotopy options, making worst-case analysis independent of RELTOL and enabling auto-convergence automatically in case of convergence failure. These options do not change the core behavior of the simulator…

We are seeing a huge trend -- the mobile revolution is changing the way we go about our everyday lives. Gone are the days where the term 'Internet'  was associated with a PC or Mac. The smartphone revolution has changed how  the data is consumed and used by consumers and businesses. For example, with the new line of smart systems, every device or appliance is connected to the Internet to manage their services in a…

TUTORIAL: Fast Track Your UVM Debug Productivity with Simulation and Acceleration

Session: 5T on Thursday, Feb. 28^th from 8:30AM - 12:00PM

For more details on the debug tutorial, click here

This debug tutorial will highlight how customers can reduce their debug turnaround time by employing the most efficient debug tools available. Class based software-oriented environments are best debugged using interactive debug techniques…

With the 16.6 release, you now have the capability of utilizing the PCB SI tools (SigXP) to work with topologies and constraints in the OrCAD Capture environment.

Capturing constraints early in design cycle is important for the following reasons:

• Quality challenges as the design cycle for any PCB product is shrinking day by day
• As the edge rates are shrinking, it is necessary to constrain the critical signals up-front to…

This month's highlighted content includes helpful information on wreal modeling, mixed-signal interoperability, verification of digitally-calibrated analog circuits, device and block-level routing and lots more.

Enjoy and don't forget to leave feedback at the top of the individual content pages in COS (Cadence Online Support) to let us know what information you find most useful.

Rapid Adoption Kits

1. Guidelines on…

Technology leaders like IBM continuously seek opportunities to improve productivity because they recognize that verification is a significant part of the overall SoC development cycle. Through collaboration, IBM and Cadence identify, refine, and deploy verification technologies and methodologies to improve the productivity of IBM’s project teams. 

Tom Cole, verification manager for IBM’s Cores group, and I took a few…

I love it when I'm sitting in a meeting with my colleagues or with a group of customers and someone brings up something about our software that they find annoying and another person says "Wait, why are you doing it that way?  Why don't you just...".  Immediately my mind says "blog time!" 

One such sequence of events happened recently around the concept of "drag and drop."  For those of…

The 16.6 Allegro Design Workbench (ADW) Configuration Manager has been enhanced!

There is an enhanced focus on software serviceability and an improved ease of use environment for managing:

• Software updates & version status
• Configuration Files & Database updates
• Single cockpit to monitor global server topology
  • Easy to use dashboard for Server connection status
• Server topology

A new ADW Server Setup Wizard provides the…

After Cadence acquired Sigrity in July 2012, we heard many of the same questions: What is happening with my favorite Sigrity tools? Is Cadence going to change the functions and features I’ve been working with several years? If I’m not a Cadence Allegro user, can I continue using Sigrity tools without purchasing any other tools? If I’m a Cadence Allegro PCB SI user, what changes am I facing now?

Everyone knows that the increasing speed and complexity of today's designs implies a significant increase in power consumption, which demands better optimization of your design for power. I am sure lot of us must be scratching our heads over how to achieve this, knowing that manual power optimization would be hopelessly slow and all too likely to contain errors.

Here are 8 Top Things you need to know to optimize your…

As described in Specman Advanced Option appnote, Specman Elite supports dynamic load and reseeding. This allows the user to run the simulation up to a certain point (often until right after reset) and save the simulation. The user can then restore the simulation and run many different tests either by changing the random seed (reseeding) or by loading additional e files which will change the test, e.g., adding constraints…