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Verification: CDNLive! Silicon Valley 2010 in the Rear-View Mirror

tomacadence

Well, we all survived another very busy CDNLive! event last week. Since I posted a preview beforehand I would be remiss if I didn't let you know what happened. The bottom line is that this was a really good show, with more than forty talks covering a wide range of EDA and EDA360 topics. The majority of these were presented by customers, with some additional sessions from Cadence management and technical experts…
- 2 Nov 2010
Verification: User Views -- Migrating From FPGA-Based Prototyping to Palladium

Ran Avinun

In recent posting published by John Cooley on Deepchip.com, users compared FPGA-based prototyping systems to Palladium systems. I always like to read responses that reflect user views -- as we all know these are always more credible.I would like&nbsp...
- 2 Nov 2010
RF Engineering: Virtuoso APS Supports RF Analyses in MMSIM 7.2 and MMSIM 10.1

Tawna
A new multi-threading capability has greatly improved simulation speed for RF Designers!
In MMSIM7.2, we introduced APS for Harmonic Balance analyses (multi-threaded harmonic balance simulation).
In MMSIM10.1, we added support for APS in Shooting PSS...
- 29 Oct 2010
System, PCB, & Package Design : A Shorter, Predictable Design Cycle for Complex PCBs -- Electrical Constraint Sets (ECSets)

hemant

This is the first in a series of blogs focused on how you can make your design cycle predictable and shorter for PCB designs that are increasing in complexity. PCB designers have to deal with increased complexities while design teams are dispersed geographically, and the time to finish the design is continuing to shrink. Some of these PCB design trends are being fueled by the desire of consumers for smaller, cheaper…
- 29 Oct 2010
Digital Design: CDNLive! Silicon Valley 2010: What EDA360 Means to Digital Implementation Engineers

BobD

CDNLive! Silicon Valley 2010 -- our user's group meeting and more -- kicked off yesterday morning at the Fairmont Hotel in San Jose, California. It's been 2 years since the last CDNLive! (last year's event was online-only) where I captured this video of our Encounter software running though VPN/VNC on an iPhone. I was thinking this morning: How are we going to top that? What is going to be the thing I remember…
- 27 Oct 2010
Verification: The Increasingly Hazardous World of FPGA Verification

tomacadence

Last week saw the publication of two interesting blog posts regarding the growing challenges of FPGA verification, first from my buddy Dave Orecchio over at GateRocket and then from my Cadence colleague Steve Leibson. Both posts made the point that FPGA developers are increasingly facing the same verification issues as developers of non-programmable devices. This trend has been evident for quite a few years, but…
- 26 Oct 2010
Verification: CDNLive! -- Israel and the U.S.

Ran Avinun

The Cadence Design Network provides a great way to learn about the latest design and verification methodologies offered by Cadence, and the ways customers are using them. I had the pleasure to attend CDNLive! in Israel last week. For me, visting Isra...
- 25 Oct 2010
Verification: Android, Linaro, and 10 Other Useful Embedded Linux Links

jasona

The state of Minnesota is unofficially divided into two parts; The Cities and The Rest of the State. Of course, The Cities refers to the Twin Cities of St. Paul and Minneapolis. Outstate people from Grand Marias to New Ulm are happy to avoid the crow...
- 25 Oct 2010
Verification: e Templates and e Macros -- An Update for Specman Users

teamspecman

A couple of recent blogs have mentioned the feature of e templates, which was added to Specman relatively recently. If you are used to e macros -- the feature that has existed in the e language almost since forever -- you may wonder if it's not just the same concept in a different form. In other words, is it really essential to use templates, when you can use macros to achieve exactly the same result?
In some sense…
- 22 Oct 2010
SoC and IP: Apple boots HDD--completely out of the new MacBook Air notebooks. SSD is the only option

archive

Claiming that the move unifies Apple’s product line, Steve Jobs yesterday announced two new lightweight MacBook Air notebook computers. Significantly, neither HDD nor optical disk storage is an internal option for these two new laptops. SSD is the only storage on offer, with capacities from 64 to 256 Gbytes. Although Jobs claims that Apple placed the SSD “right on the motherboard,” the images he showed were of a small…
- 21 Oct 2010
Verification: Team Verify at CDNLive Silicon Valley Next Week – ABV, Formal, Multi-Engine Verification and More

TeamVerify

At next week's CDNLive! Silicon Valley in San Jose, California, Cadence will cover all aspects of our verification technologies and methodologies (the agenda for Day 1 is posted here, and the Day 2 techtorials here). Of course, Team Verify will be there to support any and all events related to assertion-based verification in general, and formal and multi-engine verification in particular. Here are the specific events…
- 20 Oct 2010
Verification: A Preview of Verification Sessions at CDNLive! Silicon Valley

tomacadence

As Cadence followers well know, our annual worldwide series of CDNLive! events is a big deal both for us and for our customers. We work hard to get the best talks into the program, combining customer case studies, technical updates from Cadence experts, and the occasional partner presentation. As you might imagine, we always receive more abstracts than we can fit into the slots available, which allows the program…
- 20 Oct 2010
System, PCB, & Package Design : What's Good About Allegro Router and Via Changes? SPB16.3 Has a Few New Enhancements!

Jerry GenPart

This week, I’ll be closing discussions on the new SPB16.3 Allegro PCB Router improvements. The focus is on several enhancements for via support.

The Use_Via Rule

Many times you need to restrict the usage of specific vias in a region. Allegro PCB Router has been enhanced in the SPB16.3 release to allow via usage in a certain region. The use_via rule has been enhanced to align with the Allegro via list functionality…
- 20 Oct 2010
Digital Design: Five-Minute Tutorial: ecoAddRepeater

Kari

In today's tutorial, we're going to talk about the Encounter Digital Implementation (EDI) system command ecoAddRepeater. You may have come across this command and even used it before, or perhaps you used the GUI (Optimize->Interactive ECO...) to add buffers or inverters, and didn't know that this was the command doing the work. Either way, let's review some reasons we'd want to use such a command.…
- 19 Oct 2010
SoC and IP: Angelbird Ltd. Introduces “Wings,” a low-cost PCIe SSD for PCs. $239 for 16 Gbytes

archive

Stop me if you’ve heard this one. The fastest way to get high performance from an SSD is to bypass the disk interface and plug the SSD directly into the PC’s PCIe port. Vendors of high-performance (read “expensive”) SSDs do just that. So just where does startup (or is that “upsart”) Angelbird Ltd. get the moxie to announce a PCIe-based SSD card that sells for $239? The card is called “Wings” and is said to boot on PCs…
- 19 Oct 2010
SoC and IP: Hitachi-LG Data Storage fixes optical drive with SSD assist to use one SATA port

archive

Hitachi-LG Data Storage has updated the hybrid optical/SSD drive it announced earlier this year (How does a hybrid SSD/optical drive make sense?) by integrating the SSD with the optical drive controller and making both the optical and solid-state drives accessible through one 6Gbps SATA III port. The first-generation drive introduced earlier this year at the Computex electronics show in Taipei was essentially an SSD tacked…
- 18 Oct 2010
SoC and IP: Made in South Korea: Graphene memristor memory cells on a flexible plastic substrate

archive

IEEE Spectrum has just reported on the successful fabrication of graphene-based memory cells on a flexible plastic substrate by Sung-Yool Choi and his research team working at the Electronics and Telecommunications Research Institute in Daejeon, South Korea. The memristor memory closely resembles that of HP, using a simple crosspoint-array interconnect, with a memory cell made of graphene oxide instead of HP’s titanium…
- 14 Oct 2010
SoC and IP: Brian Fuller @EETimes: Renesas to put MRAM in 90nm microcontrollers by 2013

archive

EETimes’ Brian Fuller is blogging live from the Renesas DevCon down in southern California and he reports this morning that Renesas has announced plans to incorporate MRAM (magnetic RAM) in its microcontrollers built using 90nm process technology, with parts to be introduced by 2013. At that geometry, Renesas expects the MRAM to support 150MHz operation. Two years later using 40nm process technology, Renesas expect to…
- 13 Oct 2010
System, PCB, & Package Design : What's Good About Allegro PCB Editor Customizable Datatips? Look to SPB16.3 and See!

Jerry GenPart

In pre-select mode Allegro displays a datatip that provides information about the element that is being hovered over. The TAB key can be used to cycle through the string of elements such as symbol, pin, and net, resulting in a new display of the datatip. In the SPB16.3 release of Allegro PCB Editor, it is now possible to customize the display through a user configuration interface. Items that can be configured include…
- 13 Oct 2010
Digital Design: 3D-IC TSV Realization: The Race Has Begun!

archive

3D IC discussions are creating quite a buzz these days. No conference is complete without a mention of 3D ICs, and there are reasons behind that. 3D ICs using through-silicon vias (TSVs) help you meet challenging performance and power targets to serve the growing demands of the networking, graphics, wireless, and computing industries. And don't forget consumer needs for ultra light and thin devices!
If you have anything…
- 12 Oct 2010
Verification: Connections Partner NextOp on Assertion Synthesis and Assertion-Based Verification (ABV) with “BugScope”

TeamVerify

As anyone working in Formal and Assertion-Based Verification (ABV) knows, the task of writing assertions can quickly overwhelm even the most patient engineer. While Team Verify has partially addressed this challenge with the "Automatic Formal Analysis" capability built into Incisive Formal and Enterprise Verifier tools, our new Cadence Connections program partner NextOp with their "BugScope" tool has taken …
- 11 Oct 2010
SoC and IP: Sandforce Enterprise-Class SSD 2500/2600 processors deliver double performance

archive

SandForce has just announced a new enterprise-class SF-2000 SSD processor family including the SF-2500 and SF-2600, which deliver approximately twice the performance of the company’s existing SF-1500 SSD processor. The new SSD processors start with SATA III 6Gbps host interfaces that have twice the maximum bandwidth of the SF-1500’s SATA II interface. Maximum sequential read/write performance is now rated at 500/500 Mbytes…
- 11 Oct 2010
Verification: Video: Interview With NextOp CEO Yunshan Zhu on Assertion-Based Verification (ABV) With “BugScope”

jvh3

What makes a startup "hot"? To be sure, trade press and blogger attention helps. But from where I sit, the truly hot companies are identified by an increasing frequency of emails from Application Engineers (AEs) and Sales people to the effect of "this new company is getting traction in my accounts - users love ‘em - are we partnering with them?"
Such has been the case with NextOp Software since…
- 10 Oct 2010
SoC and IP: Anandtech reports that Intel’s new SSDs that incorporate 25nm Flash will have 4x the lifespan rating

archive

This blog previously reported that Intel will be rolling out new versions of its highly regarded X25-M SSDs. These new drives will incorporate 25nm MLC Flash devices. Now, Anandtech has reported some interesting specs. Maximum capacity is up from 160 to 600 Gbytes. Sequential read performance is unchanged at 250 Mbytes/sec but write performance will jump from 100 to 170 Mbytes/sec and the read/write IOPS ratings jump…
- 7 Oct 2010
Verification: "We Want UVM 1.0! When Do We Want it? Now!"

Adam Sherer

Short of holding signs and yelling slogans, the 12 customers I visited in the past week all declared this mantra. All are planning to move to UVM 1.0 with all of them requiring the phasing and register package capabilities, but only one also requiring TLM2 support, primarily for accessing SystemC models. The good news for them and the rest of the community is that Cadence is driving these features and more in the Accellera…
- 7 Oct 2010

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