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Sometimes these articles just write themselves... 

Last week, 3 different people asked me questions about the ADE XL Run Options form.   Sadly, the odds that 3 people in the same week would ask a question to which I actually knew the answer are vanishingly slim, so that meant I needed to do some research.  And, in the course of that research, I discovered why there were so many questions about this topic.  It is quite confusing…

The SPB16.3 release of the Allegro AMS Simulator environment contains a few additional features (which I've not yet covered in my prior posts) that I'll wrap-up in this post.

Highlighting in circuit and out files

With the SPB16.3 release, the PSpice circuit and out file syntax are presented in easy to read colors that highlight the different groups such as text, numbers, comments, expressions, operator, and keyword…

Recently there was an inquiry about the methodology for performing the f_t (transition frequency) versus Ic measurement described in my Measuring Transistor f_t blog post from July 2008:

By bid75 on September 8, 2010
I am unable to understand how ft vs. Ic...

First, I would like to introduce myself.  My name is Jim Kjellsen.  I've recently joined the Product Management group for the verification products at Cadence.  My career started as a design and verification engineer, but quickly moved over the fence to the tool provider side in EDA with Daisy Systems.  From there I moved into more of a niche EDA company, Logic Modeling, which was later acquired by Synopsys.  I had been…

A common problem when distributing engines and assertions in Incisive Enterprise Verifier (IEV) and Incisive Enterprise Manager (EMGR) at the same time using LSF with big machines is the following: if you use the "define engine auto_dist" setting, but only reserve 1 slot in LSF, then IEV will spawn off more than 16 processes within each job, overloading the machine quickly. The attention of your IT department will be…

Regular readers know that I've blogged a lot about the Open Verification Methodology (OVM) and the upcoming Accellera Universal Verification Methodology (UVM), whose 1.0 EA (Early Adopter) release is virtually identical to the OVM. I've been silent for a while, waiting for the Accellera VIP-TSC to complete the second phase of its work and release UVM 1.0, without that annoying and misleading "EA" label. In the meantime…

With the SPB16.3 release of Allegro PCB SI, there’s a new methodology for Device Modeling Language (DML) path setting and searching.

In previous releases, DML and IML paths were controlled graphically with the Library Browser, as shown below:

 
They could also be set through the use of environment variables such as signal_devlibs:

set SIGNAL_DEVLIBS /hm/test/dml/devices.dml $ALLEGRO_INSTALL_DIR/signal/cds_models.ndx

This is a guest post from JasonG at Avago. I hope you enjoy this useful piece he's contributed on using the relative-new dbTransform Encounter command.  If you'd like to write a guest post we'd love to have it.  Please drop me an E-mail if you're interested in contributing: dwyer@cadence.com -Bob Dwyer

Hello fellow digital implementation Tcl developers!  Bob asked if I'd be interested in contributing to a…

Lately the tone of the trade press and blogs about the Silicon Valley electronics industry has been largely positive.  For a variety of reasons this is a good thing, but my natural skepticism compelled me to "field check" this data with a high quality primary source: one of our crack Application Engineers (AE) who serves numerous area customers representing a broad spectrum of applications (including communications, internet…

I wanted to take a brief detour from my usual postings to point out a couple of new delivery mechanisms we're trying out for distributing video collateral -- making better use of some of those toobz on the interwebs. 

First, we've made some of the videos in the CIC Video Library at https://support.cadence.com/ available for download.  This way all the users at your site can access the videos at your convenience without…

Thanks to everyone who participated in this week's Encounter Puzzer.  If you didn't catch it earlier, have a look now before reading the solution discussion below.

I thought this puzzler was great because it's such a small and simple example, yet it leads to so many useful fundamental components of database access.  The first two comments were especially appreciated because it pointed out two of the primary ways…

Ah, the NONDEFAULT rule. This is a routing rule that is, well, not the default! It usually consists of double-wide or triple-wide metal, and at least double-wide spacing, but it can be whatever you like as long as it follows DRC rules (no violating the min or max metal widths, for example). NONDEFAULT rules are typically used to route clock nets or other sensitive nets. If you are very lucky, your tech LEF came with some…

The ability to constrain or report Differential Impedance from within Constraint Manager (CM) has been a long standing request. The SPB16.3 Allegro PCB Editor Advanced Constraints feature allows customization of a user-defined differential impedance constraint in CM.

Constraint Manager has the ability to report and Design Rule Check (DRC) single-ended impedance in the Electrical domain, Net — Routing — Impedance worksheet…