Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Academic Network: 3rd Tensilica Day in Hanover: Extending our Senses

Anton Klotz

Two events in a row are a coincidence, three events are a series. With these words Professor Holger Blume has opened the 3rd Tensilica Day at IMS Institute in Hannover and greeted more than 80 attendees, which made it the largest Tensilica-dedicated ...
- 14 Feb 2018
Breakfast Bytes: What Happens in a Patent Lawsuit?

Paul McLellan

One of the presentations in the exhibit hall, at the Chiphead Theater, was What Happens in a Patent Lawsuit? which was presented by John Strawn and Tom Millikan. I have written about patents a couple of times on Breakfast Bytes, in Patents and Standa...
- 14 Feb 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Can You Really Reduce DDR Power Dissipation by Reducing the Frequency?

References4U

In this week's Whiteboard Wednesday, Marc Greenberg examines the non-linear relationship between frequency and power consumption and the power implications of fast burst transmission vs. slow continuous transmission of data.

https://youtu.be/352-djuLWA8
- 13 Feb 2018
The India Circuit: Rural India: Technology to the Rescue?

Madhavi Rao

Last week I wrote about how mobile internet is expected to bring millions of Indians into the digital fold. Not surprisingly, there has been a spurt of tech startups focusing on the huge rural market of some 270 million, of whom about 200 million dep...
- 13 Feb 2018
Breakfast Bytes: 9½ Years to Pluto, No Go-Arounds

Paul McLellan

Here's the scene. You are Alice Bowman, who in 2018 will give a keynote at DesignCon. But that is years in the future. Today, it is 2pm on July 4, 2015. However, you don't get to eat grilled meat and drink beer since you are in the mission op...
- 13 Feb 2018
SoC and IP: See You in Barcelona at MWC!

PaulaJones

I’ve been going to Mobile World Congress in Barcelona for over 10 years, and it never fails to amaze me. This year’s theme is “Creating a Better Future” and I can’t think of a better theme for Cadence – our Tensili...
- 12 Feb 2018
Breakfast Bytes: Advanced Packaging Needs Advanced Tools

Paul McLellan

At the recent DesignCon, Cadence's John Park presented Advanced Packaging Trends and Their Impact on EDA Tools. John admitted that there were too many trends to cover so he would focus on some key areas...which, not coincidentally, are also areas whe...
- 12 Feb 2018
SoC and IP: What I Learned About System Design Enablement at DesignCon

tomhackett

While attending the recent DesignCon show for the first time, I was struck by the many displays of cables, connectors, boards, and various kinds of test equipment (you can read about the impact this had on me in my previous post, A Walk Through DesignCon Turns Into a Long Journey). There was so much hardware, in fact, that I felt like I was walking through a giant Fry’s store. The impression was so strong that my first…
- 9 Feb 2018
SoC and IP: A Walk Through DesignCon Turns Into a Long Journey

tomhackett

Have you ever attended the DesignCon show? I attended the recent event for the first time and was surprised by what I saw: tons of high-bandwidth coax cables, circuit boards, connectors, and other hardware—all harnessed to very expensive scopes and channel analyzers displaying perfect eye diagrams. This was definitely a show for hardware engineers.

Walking around the show floor brought on an unexpected feeling…
- 9 Feb 2018
Breakfast Bytes: Application Engineers Are Like Gold

Paul McLellan

I wrote recently about my experiences Running a Salesforce, and one of the key aspects of marketing in City Slickers Marketing. Today, it is time for my thoughts on application engineering. Application Engineers Application engineers are the unsung ...
- 9 Feb 2018
Analog/Custom Design: Virtuoso Video Diary: Stranded Wire – A New Sapling in Interactive Routing

Parula

In order to drive high current and to minimize routing resistivity, it is desirable to draw wide wires. But, in mature nodes, maximum width or maximum density constraints on some metal layers prevent the designers to create wide wires. Another challenge when working with designs at advanced nodes less than 22nm is that it is only possible to route with wires at minimum width. This leads to situations where the current density…
- 9 Feb 2018
System, PCB, & Package Design : SI Methodology for Multi-Gigabit Serial Link Interfaces (6 of 8)

Sigrity

Simulating with IBIS-AMI Models By this point in the process, the SerDes component suppliers should have provided any missing IBIS-AMI models, which should be updated in your simulation testbench if they exist and are available. Now the focus shifts ...
- 8 Feb 2018
Breakfast Bytes: Warsaw to Canary Islands to Madrid to Staten Island to California: Michal's Journey

Paul McLellan

Some people grow up in the US, go to high school, get into a good engineering or computer science program, graduate, and end up in Cadence. Other people take a rather more indirect route. Michal Siwinski has quite a story as to how he got from growin...
- 8 Feb 2018
Breakfast Bytes: What's For Breakfast? Video Preview February 12th to 16th 2018

Paul McLellan

https://youtu.be/wwioFa3JGuc Coming from the Cadence basketball court (camera Sean) Monday: Advanced Packaging Needs Advanced Tools Tuesday: 9 Years to Pluto, No Go-Arounds Wednesday: What Happens in a Patent Lawsuit Thursday:&nb...
- 7 Feb 2018
Breakfast Bytes: Oz and Ziyad Look to the Future of JasperGold

Paul McLellan

At last year's Jasper User Group, the two-day event was opened by Oz Levia, VP of VIP and Formal Solutions. Oz said that it was the 10th Jasper User Group, the fourth since Jasper was acquired by Cadence (I worked for Semiwiki back then and Jasper wa...
- 7 Feb 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Dual Channel DIMMs for Server Applications

References4U

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty, discusses how future server memory standards are expected to implement dual channel DIMM. Learn about how dual channel DIMMs work and what the implications are for PHY and controller IP that need to support both single and dual channel DIMM.

https://youtu.be/vilUDNv8vcI
- 6 Feb 2018
Analog/Custom Design: Integrating AMS IP in SoC Verification Just Got Easier

msteam

Typically, analog designers verify their AMS IP in schematic driven, interactive environment, while SoC designers use a UVM SystemVerilog testbench ran from a command line. In our last MS blog, we talked about automation for reusing SystemVerilog testbench by analog designers in order to verify AMS IP in exactly same context as in its SoC integration, hence reducing surprises and unnecessary iterations.

But, what about…
- 6 Feb 2018
Breakfast Bytes: Fooling Neural Networks

Paul McLellan

I wrote recently about various aspects of modeling, not just transistor models, but also deer and climate change. One of the things that I mentioned in passing was over-training. This is where the model is made so accurate, often by adding additional...
- 6 Feb 2018
Breakfast Bytes: The Old Order Changeth: Samsung Takes the Crown

Paul McLellan

The most famous line of Tennyson's poem Morte D'Arthur is "The old order passeth, yielding place to new." It is often quoted when a new king, real or metaphorical, is crowned. Last week, Intel and Samsung announced their financial ...
- 5 Feb 2018
Analog/Custom Design: Virtuosity: Sharing Custom SKILL Calculator Functions

Arja H

Have you ever written a fantastic piece of SKILL to carry out a calculation and wanted to tell the world about it? Or maybe you really need a calculator function to perform a calculation but Cadence does not supply that function with the Calculator or Expression Builder? We have a new Custom IC Calculator SKILL Function Library where you can visit and download custom SKILL scripts and upload any of your own that you…
- 2 Feb 2018
Breakfast Bytes: DesignCon: PCB and Packaging Take Center Stage

Paul McLellan

You wouldn't really know it from the name, but DesignCon is all about the design and analysis of printed circuit boards and packages. It's an exaggeration to say that IC design is never mentioned, but this is one of the premier conferences for the de...
- 2 Feb 2018
Verification: New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions

DimitryP

The recent update of the AMBA® 5 ACE/AXI specification introduces a number of significant performance improvements which help to align the protocol to the more recent AMBA® 5 CHI (Coherent Hub Interface) specification. One of the most prominent features is introduction of atomic transactions. Before we take a close look at this new class of transactions, let’s look back in time.

Previous generations of AMBA…
- 1 Feb 2018
Breakfast Bytes: DesignCon: SI, PI and EMI Have a Threesome

Paul McLellan

DesignCon 2018 opened with a keynote panel on the subject of SI, PI, and EMI Challenges Looking Ahead Through 2023. The initials are for signal integrity, power integrity, and electro-magnetic interference. Istvan Novak pointed out Amara's Law, t...
- 1 Feb 2018
SoC and IP: You Won't Believe Your Ears When Listening to Your Laptop

PaulaJones

I wouldn't believe it if I hadn't heard it myself on a laptop in the Cadence booth at the Consumer Electronics Show (CES) this year. Through a great innovation by our partner Dolby, you can now get surround sound on your laptop!

You’ve probably been in a movie theater with Dolby’s latest innovation—Dolby Atmos. And maybe you’ve purchased a television in the last year with Dolby Atmos (it was…
- 31 Jan 2018
Breakfast Bytes: Open-Source IP in Government Electronics

Paul McLellan

At the RISC-V conference late last year, one of the keynotes was by Linton Salmon titled A Perspective on the Role of Open-Source IP in Government Electronic Systems. It was not specifically about RISC-V, although the RISC-V ISA and many of the imple...
- 31 Jan 2018

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.