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Cadence has achieved a significant milestone by designing and taping out its first-ever system chiplet, marking a groundbreaking advancement in chiplet realization capabilities. Utilizing the innovative Cadence Chiplet Architecture and Framework, along with Cadence IP, EDA technologies, and select Arm IP, this system chiplet exemplifies the seamless integration of multiple chiplet dies within a single package. This pioneering…

Today’s wireless and high-speed chip designs integrate an incredible amount of functionality on very small silicon real estate. Such integration requires optimization from the early stages of the design to post-layout vs. schematic (LVS) signoff. Increasingly complex designs and advanced process nodes test the limits of electromagnetic (EM) solvers in terms of modeling capacity and times.

This blog highlights key…

In the era of Artificial Intelligence, front-end designers need a magical key to empower them with technology that enables fully optimized RTL for implementation handoff and provides RTL designers with capabilities to accurately assist in the implementation convergence process.

The magic lies with Cadence Joules RTL Design Studio, an expert system that leverages generative AI for RTL design exploration, triages possible…

An increasing number of embedded designs are multi-core systems. At the pre-silicon stage, customers use a simulation platform for architectural exploration and software development. Architects want to quantify the impact of the number of cores, local memory size, system memory latency, and interconnect bandwidth. Software teams wish to have a practical development platform that is not excruciatingly slow.

This blog shares…

The DDR5 generation of Double Data Rate DRAM memories has experienced rapid adoption in recent years. In particular, the JEDEC-defined DDR5 Dual Inline Memory Module (DIMM) cards have become a mainstay for systems looking for high-density, high-bandwidth, off-chip random access memory[1]. Within a short time, the DIMM architecture evolved from an interconnected hierarchy of only SDRAM memory devices…

In this recent Training Webinar, we explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow by guiding you through essential steps involved in creating integrated circuits—the building blocks of modern electronics.

We’ll break down the process into manageable stages, from defining the chip’s functionality to its physical realization…

As a verification engineer, you’re surely looking for ways to automate the debugging process. Have you developed your own scripts to ease specific debugging steps that tools don’t offer?

Working with scripts locally and manually is challenging—so is reusing and organizing them. What if there was a way to create your own app with the required functionality and register it with the tool?

The answer to…

Wild River Technology (WRT), the leading supplier of signal integrity measurement and optimization test fixtures for high-speed channels at data rates of up to 224G, has announced the availability of a new advanced channel modeling solution that helps achieve extreme signal integrity design to 70GHz. Read the press release.

The CMP-70 program continues the industry-first simulation-to-measurement collaboration with Cadence…