Community

Part, Schematic, Footprint and Models can all be deleted from the database now with the Allegro Design Workbench ADW16.3 release. Schematic and footprint models may only be deleted if they are not associated with a part. Once a Schematic or Footprint model is deleted from the database, the model is removed from the reference library. The deleted model archive is retained in the vault so the Librarian can check out and…

Back in 2002 and 2003 there was a lot of talk about analog synthesis being the "next new thing" to close the productivity gap between analog and digital designers. Well, I hope you didn't hold your breath for this!

That promise failed mostly because analog design was still a custom design challenge, relying on innovation to provide differentiation in the final application. Standardizing analog design…

1. Enable Enterprise MLC (multi-level cell) NAND Flash. You do…

I realized that I have just passed the second anniversary of my first blog post, which caused me to ponder a bit about this relatively new vehicle for communication. This is fair warning: some of you may find this post to be self-indulgent piffle. If so, feel free to ignore it, but you have to swear that you've never followed any of the Twitter twits who engage in self-indulgent piffle all day, every day ("I'm driving…

Sarmad Dahir of Ericsson switched from directed testing to constrained-random test generation and the metric-driven verification (MDV) flow. Constrained-random testing is much more efficient than the old directed test approach, Dahir said. "Random testing makes things easier, because you won't have to target every possible scenario."

This translates into a time savings -- perhaps 30 percent for the overall…

Just a very quick post this week on a simple, but elegant new SPB16.3 feature for the Allegro Design Entry HDL product.

Prior to the SPB16.3 release, Design Entry HDL (DEHDL) did not have the capability of drawing a new wire from an anchor point of an existing wire. Introducing the anchor point wire stretch will give an extra ease of use factor to the way the wires are connected in the schematic.

You can stretch a wire…

Hi All,

An e template (known as a parameterized type in other programming languages) is a feature that has been around for several releases and can be a great way of creating re-usable code.  Templates can be used anywhere a user would like to create a single re-useable object that might operate on different data types.  An example would be to create a scoreboard (if you were not already using the ovm_scbd package…

Don't let the name CDNLive! confuse you.  It's the Cadence user's group conference and for North America this year it's occurring in Silicon Valley October 26th, 2010.  The conference also includes Technology Demos and a Designer Expo, but the heart of the event is really the user presentations.  If you haven't submitted a paper for consideration or haven't even thought of a topic to talk about, don't worry…

As a member of the EDA community, I find it interesting and somewhat frustrating to see how much we copy each other at times. Ever notice how one company might make a position on something, and once their message resonates, then a lot of other companies come out of the woodwork with me-too messaging and positioning?

I saw this happen on mixed-signal design, and now see it happening on signoff analysis.

Here at Cadence,…

• “Experts in SystemVerilog/Specman/VERA/System C”
• “Think Verification”
• “HVL (SystemC/C++/Verilog /Vera/Specman) Experts” 

While we tweet verification-related posts whenever we come across them, if you’re on LinkedIn…

In my last post, I left you in suspense, with your mouse hovering over the words "Click to add test" in ADE XL.  Clicking on this button will bring up the ADE XL Test Editor window (which should look suspiciously familiar) and a dialog asking you to point to the design you want to use.  This design does not have to be the same cellview as the adexl view you're working with.  It can be any design you want to…

With the SPB16.3 release of PCB SI, the Model Editor has been added to allow you to view, update, and check the syntax and data integrity for various models. The first release of the model editor contains simple functions. More utilities, tools, and features will be added in future releases. 

The Model Editor is a standalone executable and can be invoked in the console. The command line syntax is:

modeleditor –v –t title…