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Latest Blog Posts

SoC and IP: Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem

MBhatnagar

Cadence tapes out 32G UCIe interface IP for high speed, highly efficient chiplet designs and demonstrate high data rate performance in TSMC's 3nm technology
- 7 Oct 2024
System, PCB, & Package Design : Using Voltus IC Power Integrity to Overcome 3D-IC Design Challenges

MSATeam

Power network design and analysis of 3D-ICs is a major challenge due to the complex nature and large size of the power network. In addition, designers must deal with the complexity of routing power through the interposer, multiple dies, through-silicon vias (TSVs), and through-dielectric vias (TDVs).
Cadence’s Integrity 3D-IC Platform and Voltus IC Power Integrity Solution provide a fully integrated solution for early…
- 7 Oct 2024
Life at Cadence: Creating Connections through Career Catalyst

Dominique Topps

Early career employees Ankit Narasimhan, Jai Ganesh Iyer, Jhenkar Kallambella Suresh, Sanjukta Sheth, Viraj Ranade, Ishika Bhattacharya, and Kushagra Gupta, hailing from Cadence’s Custom IC & PCB Group (CPG), Silicon Solutions Group (SSG),...
- 7 Oct 2024
Corporate News: First Major Toolbox for MATLAB/Simulink Model Deployment to Tensilica HiFi DSPs

Corporate

Traditionally, developing software for digital signal processors (DSPs) involves a multi-step process: crafting the algorithm code in a specialized tool, adapting it for a specific domain, and implementing it onto the DSP. Given the growing demand fo...
- 7 Oct 2024
Data Center: Tradeoffs in Managing Data Center External Airflow

NaomiM

By Matthew Kaufeler, Senior Principal Product Engineer When you build a data center, your data hall design team needs to consider how your server rack layout impacts cooling while maximizing usable space. They must plan where to place cable and pipew...
- 6 Oct 2024
Verification: Partial Header Encryption in Integrity and Data Encryption for PCIe

Kunal Chhabriya

Cadence PCIe/CXL VIP support for Partial Header Encryption in Integrity and Data Encryption.
- 6 Oct 2024
Learning and Support: Accessing Doctype Definitions in the Cadence Learning and Support Portal – pt 2

Sachin Nagpal

Hopefully, our blog Doctype definition and accessing them on Cadence Learning and Support Portal -1 was useful for you, and as promised, we are excited to present some other collaterals within our Cadence Learning and Support Portal (all listed under...
- 4 Oct 2024
Computational Fluid Dynamics: Deciphering the Potential of High-Fidelity CFD Simulations Across Industries

Veena Parthan

The landscape of CFD is undergoing a novel shift with the emergence and application of high-fidelity simulations. These advanced simulations, particularly through large eddy simulations (LES), are setting new benchmarks in precision, accuracy, and efficiency across various industries.
- 3 Oct 2024
Data Center: CadenceCONNECT: Take the Heat Out of Your AI Data Center

NaomiM

As we delve deeper into the AI era, data centers have become the backbone of technological progress. These high-density computing hubs, often called “AI factories,” are crucial for sustaining and accelerating advancements across various f...
- 3 Oct 2024
Corporate News: International Women in AI Day: Creating More Opportunities for Women in AI

Corporate

In the rapidly evolving world of artificial intelligence (AI), diversity is not just a value—it's an imperative. International Women in AI Day, celebrated on October 1, shines a spotlight on the contributions and challenges faced by women ...
- 1 Oct 2024
Analog/Custom Design: Doc Assistant A-Z: Making the Most of the Cadence Cloud-Based Help Viewer Part 3

Priya Sriram

Welcome back to the Doc Assistant A-Z blog series!

Since the launch of Doc Assistant, we've been gathering feedback and input from our customers regarding their experiences with our latest documentation viewer. My interaction with Ralf was particularly useful and interesting.

Ralf is a design engineer who works on complex schematics and intricate layouts. For each release, he is challenged with the task of verifying…
- 30 Sep 2024
Analog/Custom Design: Spectre 24.1 Release Now Available

SpectreReleaseTeam

The SPECTRE 24.1 release is now available for download at Cadence Downloads. For information on supported platforms and other release compatibility information, see the README.txt file in the installation hierarchy.
- 30 Sep 2024
SoC and IP: Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA

Nayan Gaywala

Today's high-performance computing systems often require the designer to instantiate multiple CPU or DSP cores in their subsystem. However, the performance gained by using multiple CPUs comes with additional programming complexity, especially when accessing shared memory data structures and hardware peripherals. CPU cores need to access shared data in an atomic fashion in a multi-core environment. Locking is the most…
- 30 Sep 2024
Verification: Jasper Formal Fundamentals 2403 Course for Starting Formal Verification

Amey Dahikar

The course "Jasper Formal Fundamentals v24.03" introduces formal analysis to those who want to use formal analysis for design or verification.

To optimally benefit from this course, you must already have sufficient knowledge of the System Verilog assertions to be capable of writing properties for formal verification. Hence, this training provides a module on formal analysis to help cover this essential background…
- 30 Sep 2024
Computational Fluid Dynamics: Highlights from the CadenceLIVE India CFD Track

Veena Parthan

On September 13, CadenceLIVE India marked its second successful year in the computational fluid dynamics (CFD) domain, featuring an insightful CFD track at the Radisson Blu Hotel, Bangalore. The event showcased Cadence's remarkable expansion beyond ...
- 26 Sep 2024
System, PCB, & Package Design : 10 Most Viewed Posts in Cadence Community Forum

Renu Vibha

Community engagement is a dynamic concept that does not adhere to a singular, universal approach. Its various forms, methods, and objectives can vary significantly depending on the specific context, goals, and desired outcomes. Whether you seek assis...
- 25 Sep 2024
Corporate News: Transforming Drug Discovery with Computational Methods

Reela Samuel

The recent pandemic has highlighted the critical need for rapid and cost-efficient development of new medications. However, creating new drugs—whether small molecules, biologics, macrocycles, or degraders—is a lengthy and costly endeavor,...
- 25 Sep 2024
Verification: DDR5 UDIMM Evolution to Clock Buffered DIMMs (CUDIMM)

Shyam Sharma

DDR5 is the latest generation of PCDDR memory that is used in a wide range of application like data centers, Laptops and personal computers, autonomous driving systems, servers, cloud computing, and gaming are now increasingly being used for AI applications with advances in memory bandwidth and density to allow DDR5 DIMMs (Dual Inline Memory Modules) to support densities higher then 256 GB per DIMM card. The highest speed…
- 22 Sep 2024
Life at Cadence: Cadence Employee's 4,260km Walk to Support the Fight Against Cancer

Lautanen

Pierre-Alexis Desmares, Principal Applications Engineer at Cadence from France, is taking on a challenge by hiking the Pacific Crest Trail (4,260 km) within the USA alone, raising €1 per km for the League Against Cancer. You can donate here for ...
- 19 Sep 2024
Computational Fluid Dynamics: Improving Mesh Adaption with Fidelity CFD

Veena Parthan

This blog post explores the concept of mesh adaptation and the latest mesh adaptation features in Fidelity 2024.1, discusses its benefits, shares best practices, and highlights important considerations when using mesh adaptation in Fidelity 2024.1.
- 18 Sep 2024
Corporate News: Introducing Fem.AI: Reshaping the Tech/AI Workforce for a More Equitable Future

Nicole Johnson

The Cadence Giving Foundation was founded in 2022 to support critical needs in communities around the world with a focus on access to STEM education, DEI in STEM, and climate and sustainability. We are excited to unveil an exciting initiative our tea...
- 18 Sep 2024
System, PCB, & Package Design : DesignCon Best Paper 2024: Addressing Challenges in PDN Design

NaomiM

Explore Impacts of Finite Interconnect Impedance on PDN Characterization

Over the past few decades, many details have been worked out in the power distribution network (PDN) in the frequency and time domains. We have simulation tools that can analyze the physical structure from DC to very high frequencies, including spatial variations of the behavior. We also have frequency- and time-domain test methods to measure the…
- 17 Sep 2024
Corporate News: Cadence Tensilica HiFi 5 DSPs Used in NXP’s Next-Gen Audio DSP Family

Corporate

In a significant achievement for the automotive industry, Cadence's Tensilica HiFi 5 Digital Signal Processors (DSPs) are now a key component in NXP® Semiconductors' latest automotive audio DSP family, enabling advanced audio capabilities for nex...
- 17 Sep 2024
Digital Design: The Best Way to Learn – Cadence Cerebrus AI-Driven Design Implementation

Michal Bleich

The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cadence Cerebrus will intelligently optimize the Cadence digital full flow to meet the power, performance, and area (PPA) goals in a completely automated way. Use Cerebrus Apps to optimize some aspects of the design as well.

Running…
- 16 Sep 2024
Digital Design: Conformal ECO Designer

FormerMember

Conformal ECO Designer enables you to implement RTL engineering change orders (ECOs) for pre- and post-mask layout and offers early ECO prototyping capabilities for driving critical project decisions.

Conformal ECO compares two designs and generates a functional patch that implements the changes between the two designs.

One major criterion for determining patch quality is whether the patch can meet timing closure. To…
- 15 Sep 2024

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