Find Other Members ►

Get email delivery of the Cadence blog (individual posts).

Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Verification: CXL Enumeration: How Are Devices Discovered in System Fabric?

Sangeeta Soni

PCIe designed system fabrics rely on software enumeration by Operating System (OS) for device discovery. CXL 2.0 device is exposed as PCIe native endpoint and CXL 1.1 is exposed as root complex integrated endpoints (RCiEP) during software enumeration process. Notably, there is a difference between the discovery of CXL 1.1 versus the CXL 2.0 device. Hence, the configuration space for CXL1.1 and CXL 2.0 varies. In this…
- 27 Oct 2022
Life at Cadence: Making Sustainable Data Center Design Possible with Digital Twins

Nimish Modi

Cadence has expanded into the realms of systems design and computational fluid dynamics (CFD). Cadence’s acquisition of Future Facilities, a pioneer in the data center digital twin space, expands our CFD and thermal analysis portfolio and extends it to data centers. In addition to electronics cooling analysis, Future Facilities’ innovative solutions enable customers such as Thésée DataCenter, Digital Realty, and Equinix…
- 27 Oct 2022
Life at Cadence: CalSol Is Paving the Way for Solar Vehicles

Corporate

CalSol is on a mission to design, build, test, and race the world’s fastest and most solar-efficient vehicles. A team of undergraduate students from the University of California, Berkeley, CalSol was founded in 1990, and since then, they have b...
- 27 Oct 2022
Breakfast Bytes: PACMAN and Using Jasper for Security Verification

Paul McLellan

At the recent Jasper User Group meeting, there were a couple of presentations on using the Jasper apps for security verification, specifically Jasper SPV (for Security Path Verification): HW Security Path Validation Using Formal Methods: Intel ...
- 27 Oct 2022
RF /マイクロ波設計: μWaveRiders:Cadence AWR Design Environment V22.1 ソフトウェアのリリースをハイライト

RF Design Japan

The Cadence AWR Design Environment V22.1 production release is now available for download at Cadence Downloads with design environment, AWR Microwave Office, AWR VSS, AWR Analyst, and other enhancements.
- 26 Oct 2022
Breakfast Bytes: TSMC OIP: N3E/N4P, 3DFabric, Analog Migration

Paul McLellan

Today, it ia TSMC's OIP, the Open Innovation Platform Ecosystem Forum. I will write about some of what was said there soon. But in the meantime, as usual, Cadence has made several announcements jointly with TSMC. N3E and N4P Node Certification T...
- 26 Oct 2022
RF Engineering: μWaveRiders: Cadence AWR Design Environment V22.1 Software Release Highlights

TeamAWR

The Cadence AWR Design Environment V22.1 production release is now available for download at Cadence Downloads with design environment, AWR Microwave Office, AWR VSS, AWR Analyst, and other enhancements.
- 26 Oct 2022
Computational Fluid Dynamics: On-Demand Webinar - Reduce Ship Fuel Emissions and Costs Through CFD Optimization

AnneMarie CFD

Ship designs, made in CAD software, are becoming more complex every day, and CFD tools have become commonplace to optimize vessel design and reduce lifetime fuel emissions and costs as much as possible.
- 26 Oct 2022
Computational Fluid Dynamics: Women in CFD with Shi Yee Lim

Veena Parthan

The Women in CFD series highlights the career expedition of women in computational fluid dynamics (CFD). For this article, I spoke with Shi Yee Lim, Principle Product Engineer at Cadence, to learn a little about herself, her career journey as a product engineer, and a few tips to the women in or interested in CFD out there!
- 26 Oct 2022
Cloud: For Advanced Chip Design, It’s Time To Go Cloud-First

Mahesh Turaga

EDA in the cloud is on the cusp of mass adoption. Semiconductor companies big and small are today embracing SaaS EDA design and discovering significant productivity and scalability benefits in doing so. This wave of cloud adoption is being driven by...
- 25 Oct 2022
Breakfast Bytes: Jasper User Group 2022: Ziyad's SOTU

Paul McLellan

This year's Jasper User Group meeting took place last week. As usual, the meeting was opened by Ziyad Hanna's presentation on the state of the formal. This year, he titled his presentation Formal Verification in the Era of Domain-Specific Computing. ...
- 25 Oct 2022
Verification: DisplayPort (DP) Tunneling over USB4

tfox

USB4 is an industry standard that tunnels three different protocol specifications (PCIe, USB3 and DisplayPort) serially to a destination. DisplayPort (DP) tunneling over USB4 means DP protocol packets are converted into USB4 protocol packets and transferred over its fabric to a destination. Before the USB4 router sends the packets to its destination, they are converted back to DP protocol packets. In sum and substance…
- 24 Oct 2022
Computational Fluid Dynamics: Last Week at Fidelity CFD

John Chawner

Good morning and welcome to the last full week of October. Before we plunge into November, let's review what happened at Fidelity CFD last week. From the Blogs Streamline Reading and Writing Files from Fidelity Pointwise For a CFD solution, a CA...
- 24 Oct 2022
Breakfast Bytes: IEDM and RISC-V Summit 2022 Previews

Paul McLellan

There are two big events coming up in the first couple of weeks of December. IEDM is in San Francisco from December 3-7 (the conference proper starts on the 5th, with tutorials and short courses at the weekend. See below for more details). The follow...
- 24 Oct 2022
Verification: Demystifying PCIe Lane Margining Technology

mrana

Lane Margining which was introduced in PCIe 4.0 and has been a very important technology since then. With the doubling of the bandwidth from 8 GT/s to 16 GT/s per Lane in formulating the PCIe 4.0 specifications, there arises the need-to-know overall link health as channels are pushed near operating limits by frequency doubling. By link health I mean -how much signaling margin is available in the design to squeeze out full…
- 21 Oct 2022
Breakfast Bytes: Cadence, McLaren, and the United States (Austin) Grand Prix

Paul McLellan

As you probably know, Cadence has a technology partnership with McLaren racing. I wrote about it when we announced it in my post Cadence Shifts into High Gear with the McLaren Formula 1 Team. If you live in the U.S., this weekend is one of the big ev...
- 21 Oct 2022
Life at Cadence: Building Confidence through the Cadence Returnship Program

Michelle Hoffmann

Re-entering the high-tech field after taking a break to prioritize family can be overwhelming. When Sanjita, Lead Application Engineer and Cadence Returnship alum, was ready to re-enter the workforce, she had to learn to navigate new technological de...
- 20 Oct 2022
System, PCB, & Package Design : Cadence OrCAD and Allegro 22.1 is Now Available

AllegroReleaseTeam

The OrCAD® and Allegro® 22.1 release is now available at Cadence Downloads. This blog post contains important links for accessing this release and introduces some of the main changes made and the new features that you can look forward to.

OrCAD/Allegro 22.1 (SPB221)

Here is a representative list of the changes and enhancements across products with brief overviews.

Allegro PCB Editor and Allegro Package Designer…
- 20 Oct 2022
Life at Cadence: IQM Is Building the Next Generation of Quantum Computers

Corporate

IQM seeks to solve one of the greatest technological challenges globally: building useful quantum computers. A spinoff of Aalto University and VTT Technical Research of Finland, IQM’s been a key player in Europe’s quantum ecosystem, havin...
- 20 Oct 2022
Life at Cadence: RISC-V Is Thriving – Here’s What You Need to Know

Corporate

RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength. The RISC in RISC-V stands for Reduced Instruction Set Computer, meaning it’s designed to simplify eac...
- 20 Oct 2022
Breakfast Bytes: Latinx Heritage Month

Paul McLellan

Last week, Cadence held a Mercado Fiesta on the campus to celebrate Latinx Heritage Month. Latinx Heritage Month runs from September 15 through October 15, so it's now over. But I'm going to write about it today anyway. The celebration ...
- 20 Oct 2022
Analog/Custom Design: Start Your Engines: Clone your AMS Designer Testcases and Rerun them Anywhere

Andre Baguenie

Design Capture and Packaging (DCP) utility lets you isolate, capture and package the source files easily from your Spectre AMS Designer testbench and immediately rerun it in the same or a different environment. Check out this blog to know more.
- 20 Oct 2022
Digital Design: HLS for AI/ML Models: TensorFlow to RTL

Vinod Khera

Artificial Intelligence (AI) plays a key role in semiconductors to meet the challenging demand and rising customer expectations. But implementing these AI models in Hardware (FPGA) is challenging. AI developers generally use TensorFlow/Caffe model, w...
- 19 Oct 2022
Computational Fluid Dynamics: Augment Certainty of Bio-simulation Studies with Computational Fluid Dynamics

Veena Parthan

Computational fluid dynamic (CFD) simulations have a lot to offer for a top-level view of how the flow of different fluids can affect the drug delivery process or other bio-simulation studies for lead discovery.
- 19 Oct 2022
カスタムIC／ミックスシグナル: Spectre Tech Tips: ダイナミック電流密度チェック

Custom IC Japan

デバイスと回路の信頼性は、個々のMOSFET デバイスが短時間に消費する電力と、発生する熱の量に大きく依存しています。信頼性と寿命を向上するために、回路設計者はデザイン内のデバイスの消費電力を最適化する必要があります。Spectre 21.1 ISR10以降では、電力密度が大きいMOSFETデバイスを検出するための、新しい過渡ベースの手法がシミュレータによって提供されます。この動的なデザインチェックは dynamic power density check と呼ばれます。こ...
- 19 Oct 2022

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.