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Monday: Lip-Bu Tan is honored by GSA with the Maurice Chang Exemplary Leadership Award

Tuesday: IEDM, the International Electronic Devices Meeting. I'll cover some of the advanced process announcements.

Wednesday...

The Sunday of IEDM there were two all-day short courses. The one I attended was Technology Options for the 5nm Node. It was organized by An Steegen of imec. I am not going to attempt to cover the entire day's presentations in a short post like this, but...

In this week's Whiteboard Wednesdays video, the last of a 3-part series, Lana Chan discusses the evolution of PCI Express and the changes associated with PCIe Gen 4.

https://youtu.be/fHaAyK1OMls

You must have come across and experienced the capabilities of Pin to Trunk routing and its robust features. The Pin to Trunk routing connects an individual pin to a trunk. This routing style is usually used when a spine structure is required.

With complex and large designs, there are large array of pin connections. At times, while routing we encounter issues with the array of pin connection. Have you ever thought:…

We all know the futuristic vision of the world just around the corner. The vision where we tell our smart home that we’ve just left work at the end of a long day, and we’re heading home. Our home then tells the thermostat to warm up or cool down, lights to turn on, and the oven to start baking the lasagna we left in it that morning. We arrive to a warm, brightly lit home, and hot, freshly cooked food.

You…

I wrote recently about Eben Upton's presentation about the genesis of business-card-sized Raspberry Pi, and how they went from optimistically hoping to sell 10,000 to surpassing 10 million three months ago. If you don't know what Raspberry Pi is, then...

One of the announcements at the recent RISC-V workshop was by SiFive. This is the company started by the creators of the RISC-V instruction set architecture (Krste, Andrew, and Yunsup) to commercialize silicon implementations.

Four months ago, at the...

We'd like to welcome guest writer Yanyan Qiao from our Cadence Japan AE team.  Many thanks for her contribution!

Today analog design has become very challenging. Analog circuit designers need tools which can provide deep insight into circuit behavior. The MMSIM simulator family provides device check functions, as well as static circuit topology checks and dynamic behavior check functions for typical design problem…

The fifth (V^th?) RISC-V workshop took place this week at Google in Mountain View. This was actually the third workshop this year. Rick O'Connor, the executive director of the RISC-V foundation, opened the meeting. "It's been quite a year," he said, giving...

https://youtu.be/IAPCDXodsno

Monday: James Adams of the Raspberry Pi foundation talks about how Cadence PCB tools were used to design the Raspberry Pi

Tuesday: At the recent RISC-V workshop, SiFive announced the first commercially available RISC-V ...

At EDPS back in May (yes, I know I'm behind), Andrew Filo talked about Building the Internet of Space (IOS). He is an independent consultant but works with places like NASA Ames and was a consultant on the 3D printer in the ISS. What he was really...

Some things are best described with tables—each column shows the values for one category, and each row encapsulates one given set of values for all categories. e verification language code is a perfect fit.

This blog describes how to use tables in your verification environment code to make the code more readable and more easily maintained. The tables can be written in the code or they can be pulled in from an external…

I attended a recent workshop on Protium titled Accelerating Embedded Software Development: Protium—Ease of Use in FPGA-Based Prototyping. By the way, Protium really is a word, used in chemistry and physics when they need to specify the isotope of...

Tired of struggling with pairing your Bluetooth devices and getting them to work with each other? In this week’s Whiteboard Wednesdays video, Scott Jacobson explains how Bluetooth 5 does away with this and other range limitation problems and makes connecting your mobile devices seamless.

https://youtu.be/qEA9OYRifWo

There is an Accellera working group that is developing a portable stimulus standard. Like any Accellera group, it contains vendors and users so that both communities are represented.The working group is chaired by Faris Khundakjie of Intel, the vice-chair...

Soon it is the International Electron Devices Meeting. It takes place in San Francisco Hilton Union Square (which is actually not in Union Square but on O'Farrell Street a couple of blocks away). It is from December 3rd to 7th. So it starts next weekend...

https://youtu.be/CUGTiPJQjuI

Monday: My preview of IEDM which includes 7nm from TSMC and from GF/Samsung/IBM

Tuesday: The portable stimulus standard (PSS), which Cadence is deeply involved with

Wednesday: Protium, Cadence's FGPA prototyping...

It’s Thanksgiving! Happy Thanksgiving if you are reading this on the day. Cadence is closed, of course. But here is a post anyway. This has nothing to do with EDA or the semiconductor ecosystem or even Cadence. It is also a puzzle and an important lesson...

Have you ever come across a situation where you have a test setup in ADE Explorer and you need to create similar setups with slight variations and then save them in different cellviews? 

Before starting with this task, the first thing that strikes anyone’s mind is to find out a way that can help avoid hassles of doing the same task again and again. 

Virtuoso ADE Explorer brings to you the ability to save the current…

Allegro PCB Editor now offers Rigid-Flex applications where it’s common to have different fabrics across the final PCB product. The new functionality offers integrating more technology into less material space. This technology enables design flexibility way beyond conventional rigid interconnect methods. Rigid-flex consists of flex circuit(s) that are laminated within a rigid dielectric material. Base Material for flex…

There was a recent panel discussion at Cadence on the future of EDA. The panelists all got to have their say first. You can read about that in the last two days' blog posts: The Future of EDA: The View from Academia and Future of EDA: Industry, Well...

There was a recent panel discussion at Cadence on the future of EDA. If you didn't see it, then read yesterday's post first, which introduces everyone and has the view from academia: The Future of EDA: The View from Academia.

There was a recent panel discussion at Cadence on the future of EDA. Of course the E in EDA stands for electronics, but that's far too boring in the IoT era, so everyone called it the "cyber-physical" domain. To be fair, that fitted with the academics...