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https://youtu.be/KKiIDaN-3CE

Monday: At CDNLive Boston I moderated a panel session with east coast experts on Signal and Power Integrity.

Tuesday: I present the highlights of MIPI's first developer conference, as MIPI transitions from being mobile-only...

At CDNLive in Boston, Andrew Ross of AMD presented a wealth of practical information about how best to use emulation.

He broke things down into four main areas: hardware systems, workflow, stimulus, and design. He pointed out that there are really two...

In EDA you traditionally have to know several modelling languages for several domains. One of those domains is functional verification. In functional verification you will be working with Hardware Design Languages (HDLs), Hardware Verification Languages...

IEEE 802.3 is the standard number for various flavors of Ethernet. With Ethernet constantly increasing its speed for use in data centers, Ethernet moving into vehicles, power over Ethernet, and Ethernet over various media, there is a lot of work going...

In this week's Whiteboard Wednesdays video, Michelle Mao follows up on last week's video and takes a closer look at Hierarchical CNN and how to train different networks for family and member classification.

https://youtu.be/WzPcECV5Uqs

At CDNLive Boston, the invited keynote was by Dr. Bill Chappell of DARPA's Microsystems Technology Office. Since he took the position in mid-2014, he has focused the office on three key thrusts important to national security. These thrusts include ensuring...

Way back in 2006, Luciano Lavagno, Lou Scheffer, and Grant Martin, all then at Cadence, edited a two-volume book on EDA. The first volume covered EDA for IC System Design, Verification and Testing. The second volume covered EDA for IC Implementation,...

In Barcelona in February I attended a "keynote' with Mark Zuckerberg which was actually an on-stage interview. To read what I said about it then, look at MWC: Zuckerberg Interview. One of the points he made there is that half the world needs...

https://youtu.be/eDeD0mg7D54

Monday: My review of Electronic Design Automation for IC System Design, Verification and Testing, and Electronic Design Automation for IC Implementation, Circuit Design and Process Technology. This is the second edition of...

I talked last week to Kevin Yee, Sachin Dhingra, and Moshik Rubin about the history of MIPI, Cadence's involvement with MIPI, and the upcoming MIPI DevCon that will take place on September 14 and 15 at the Computer History Museum in Mountain View. Steve...

https://youtu.be/a1jrsatZ5f0

A couple of weeks ago I talked to Krste Asanović and Jack Kang of SiFive. Jack is the VP of product and business development. Krste is the chief architect, and, of course, the leader of the team at UC Berkeley that defined the RISC-V ISA (although he...

Use teamwork to get off the critical path!

When (not if) change happens or scope creeps... the PCB design team is always on the critical path. You can answer this schedule challenge by dynamically scaling resources with the new concurrent team design capabilities in the Allegro 17.2 2016 Release. We created this product offering to provide designers with a quick an easy way to share a common Allegro database to perform…

Lots of documents are posted on Cadence Online Support on regular basis. Let us take sneak preview of recently published documents. You can access the database by logging onto https://support.cadence.com/.

Allegro PCB Librarian XL Tutorial
This tutorial will guide users through a tour of developing library data utilizing PCB Librarian XL. You will review symbol development and the associated…

CDNLive Boston took place last week. It is really CDNLive East Coast, and there were plenty of people who had come from further afield, such as Florida and North Carolina. I came from California, along with many of the corporate marketing team that run...

I've been writing quite a bit about RISC-V (pronounced "risk five") since I think that it is going to turn out to be very significant, although it is still early days. However, momentum is truly building behind the instruction set architecture (ISA)....

Last year was the 50th anniversary of Moore's Law. One consequence of Moore's Law has been that computers got significantly faster on a regular basis. Until comparatively recently, when computers by and large were all "fast enough", we would all replace...

If you’re anything like me, you’ve spent the last couple of weeks glued to the TV, watching the 2016 Olympics in Rio, cheering madly every time a favorite athlete was competing. In our household, the entire family gathers around our big-screen TV every evening, and as Olympic events are wont to be, most photo finishes are endlessly paused, still-forwarded, verdicts passed and debated. Time and again, I’m simply astounded…

https://youtu.be/lD8VFUNds7o

Monday: Labor Day.

Tuesday: CDNLive Boston. I report from last week's CDNLive Boston with a summary of some high spots of the day.

Wednesday: SiFive, a look at the fabless semiconductor company created by the creators...

The MIPI Alliance exists to standardize widely used interfaces in mobile, such as those to cameras, displays, sensors, and more. I think MIPI originally stood for mobile industry processor interface when it was created, but now it says that "MIPI is not...

Are you an advanced node layout or CAD engineer trying to find a methodology for routing designs in the Virtuoso platform? Interested to learn how to specify tracks for correct-by-construction designs using width spacing patterns (WSPs)? If you are not using the WSP Manager in the Virtuoso environment to create and modify your WSPs, now is the time to try it.

Who?

Istvan Novak - senior principal engineer at Oracle

Kevin Roselle - senior staff engineer at Qualcomm

Dale Becker – chief electronics packaging engineer at IBM

Stephen Scearce – senior manager of high-speed design at Cisco

Ken Willis - product engineering director of high-speed analysis products at Cadence

What?

Our experts got together and agreed on a set of kickoff topics. These are issues…

At CDNLive in India, Cadence's Hany Elhak discussed aging and self-heating, and how to analyze it.

All transistors age and all transistors have self-heating effects. However, aging wasn't really an issue until 28nm. 90nm transistors will last essentially...

Microsoft provided details of their HoloLens HPU at HotChips this week, revealing the use of 24 optimized Tensilica processors to speed up all the sensor processing by up to 200x. The media has taken notice as well with reports appearing across all of the popular sites.

What Microsoft did sounds pretty extreme; creating a processor to make it run their algorithms in fewer cycles so as to keep both the performance high…