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What happens when you challenge a group of electrical and computer engineering students to come up with the most innovative and imaginative product with just a handful of electronic parts, miscellaneous items, limited funding and tight deadlines?  Bui...

Today Cadence announced the latest product in the "us" series of next-generation tools for leading-edge nodes, the Modus Test Solution. I always think that test gets treated as a second-class citizen, but in fact it is a major contributor to the cost...

Documentation plays a significant role in helping to understand the software. Cadence is putting in lots of effort in developing different forms of documentation, from product manuals to videos, application notes, tutorials, Rapid Adoption Kits (RAKs), and point solutions. We are kicking off a new series to highlight interesting and useful content which gets added to Cadence Online Support.

Types of documents on Cadence…

Here at Cadence we are very proud to provide internships to students and graduates, and offer them the opportunity to develop skills within a successful and dynamic workplace. Here are three accounts from previous IT interns who have now progressed into...

We enjoyed sharing our latest news with the many people who visited our booth at this year's DesignCon, showing our demonstration of PCIe 4.0 carried on a 16Gbps Multi-Protocol PHY. You can see some of the demo in this ChipEstimate.TV video.

Visitors most valued the performance of the 16Gbps Multi-Link PHY. In addition, attendees were very interested in:

• PCIe 4.0 and 10G-KR support: Yes! Our product does support…

There is a law in business organization known as Conway's Law. This states that:

Organizations which design systems...are constrained to produce designs which are copies of the communication structures of these organizations.

The law was stated...

Moore's Law is in the news again since Intel, having maintained for years that nothing is slowing down, finally showed what they really think. It is a golden rule in economics to look at what people do and not what they say, what is known as "revealed...

Abu Dhabi, the capitol of United Arab Emirates (UAE), has a vibrant academic scene with respect to microelectronics. The founder of UAE, Sheikh Zayed bin Sultan Al Nahyan, was convinced that, "the best investment of our wealth is in creating cultured and...

I always find DesignCon a slightly weird conference to attend. I swim in the semiconductor world like a fish swimming in the ocean, and I rarely notice there is land out there too. DesignCon is the conference beyond the chip, about boards. To the extent...

In this week's Whiteboard Wednesdays video, Chris Rowen takes a closer look at the key metrics for embedded neural networks and what today's devices need to do to collect this sophisticated data.

https://youtu.be/2m9-qRlhGLQ

The current 16.6 HotFix now provides support for the Altium to Allegro PCB Editor Translator. The translator will convert both PCB and schematic files into Allegro PCB Editor and Allegro Design Entry HDL (DEHDL) files. Look to a future HotFix for the availability of the Altium to OrCAD Capture schematic translator.

In Allegro PCB Editor under the File menu select Import,…

You can't go for very long without hearing about the Internet of Things (IoT) in general, and wearables in particular. The biggest segment of wearables is fitness trackers that measure your activity, sleep patterns, heart rate, and perhaps other things...

At IEDM in December, there was a full-day course looking at the options for transistors and interconnect for the 5nm node. The academics opened the show with Mark Lundstrom presenting on behalf of a team from Purdue, MIT, and NYU on Device Options and...

The Allegro PCB Editor 16.6-2015 release (requires login) now provides support for differential pair return path vias, a method to add return path vias to a differential pair easily during the Add Connect command. Return path vias are also referred to as ground reference vias or stitching vias. They provide a current return path to minimize signal degradation in PCB and packaging interconnects by adding additional via…

To support academia using the latest industry-standard tools, Cadence's Genus Synthesis Solution has been made available to universities. If you want to use the Genus solution, please contact the Cadence university partner in your region or write an email...

Most, if not all, designs which are being verified today are configurable. This is just a fact of life, with companies trying to reuse as much IP as possible in multiple different projects, or iterations of the same project. The requirements change as well (sometimes too often) and the interface protocols are getting more elaborate and layered. Just have a look at the table below:

(Ref: http://www.3gpp.org The Mobile…

The most important new connector in town (especially if that town was Las Vegas during CES) is the new USB Type-C connector. The reason it is so important is that it has the potential to be the universal connector. Of course it replaces the old USB Type...

In this week's Whiteboard Wednesdays video, Neil Robinson follows up on last week's “SSD Controller Basics and Trends” video to show how optimizing Tensilica processors for use in SSD controllers meets the high performance and low energy consumption trend and yet provides full flexibility through programmability with lower development risk.

https://youtu.be/5CvplrV6oa4

On February 9, Cadence is hosting an all-day Embedded Neural Network Summit., with a focus on "Extending Deep Learning into Mass-Market Silicon." It will take place in the building 10 auditorium on the Cadence campus at 2655 Seely Avenue, San...

PCIe Gen4 is bringing new possibilities to servers and virtualization. The interface increases the bandwidth and value of data transmission from server to server, switch to switch, and server to storage, enabling even larger dataset analysis and other complex cloud services.

High-speed SerDes technology is used to implement these high-speed connections, often at advanced nodes such as 14/16nm. To be sure, it's becoming…

In any advanced node, one of the most important pieces of IP is a high-performance SerDes PHY. Of course, what counts as high-performance depends on the node. At the current 16nm node, 16Gbps is the sweet spot. The reason that SerDes is so important is...

Mobile Unleashed is subtitled The Origin and Evolution of ARM Processors in Our Devices. It is by Don Dingee and Dan Nenni (my collaborator on our book Fabless). They even persuaded Sir Robin Saxby, ARM's founding CEO, to write the foreword. It is not...

Cadence was at CES last week showing the most recent additions to their vision, audio, and USB IP solutions. Sometimes these types of shows seem a little bit like the nursery rhyme:

This is the cat,
That killed the rat,
That ate the malt,
That lay in...

In this week's Whiteboard Wednesdays video, Neil Robinson talks about SSD controllers, showing the functionality basics and trends for increasing the performance and lowering the energy consumed while adding more processors for flexibility.

https://youtu.be/bu4saRek7QM