Community

My colleagues on the Verification IP team have been honored to present at the annual "IP '08" conference this week in Grenoble, France.  Unfortunately for me I'm not able to attend (hence no photo blog or video; sorry), but my colleague Pete Heller in the Verification IP group has offered to relay the following news about this growing event.

Q. [Joe] What is IP'08?
A. [Pete] IP'08 is an annual…

SoC-Encounter has automatic partition pin assignment capabilites.  The tool also allows us to provide guidance on where partition pins should/should not be allowed to go.  However, it is sometimes useful for certain pins to be placed at certain coordinates, layers, and/or order.  When this level of control is needed, the Pin Editor can help automate the task of moving pins to their desired locations.  This demo shows…

Just a quick follow-up to my previous interview with Henry Von Bank of Posedge Software. Henry informed me that they are offering ISX consulting services for companies that could use some additional resources integrating and deploying ISX. There is a data sheet with more details and contact information.

It's been a year since I heard the first solid report about Synopsys supporting the e language (IEEE 1647-2008) natively inside VCS.  (Note a key distinction here: VCS has interfaced with e language and/or Specman-driven testbenches for years -- that's not what I'm referring to.  The issue here is VCS running e code natively like it runs Verilog natively.)  In the past year I have had many more anecdotes…

New functionality has been added to the SPB16.2 Allegro Advanced Package Designer (APD) suite of tools to support Advanced Plating Bar Checks.

Posedge Software is a Cadence Verification Alliance Member with skills in two of my favorite areas: virtualization and embedded software verification. Posedge has worked with ISX as far back as 2006. Besides the fact that they are skilled in verification I must also mention that they are from Minnesota, mostly to prove that my home state is not a complete wasteland and other smart people also live here (even though…

Last week I had the pleasure of attending a DV Club lunch presentation from Dr. Henry Chang of Designers' Guide Consulting on "What the Digital Verification Engineer Needs to Know about Analog Verification".

The talk was very engaging, where Dr. Chang's comments on the relatively primitive state of analog verification confirmed my observations in talking with customers and Trailblazer partners…

• Add Via Overview…

I've really been enjoying the discussions in our Digital Implementation Forums.  Thanks to those who have contributed questions and answers, and to you "lurkers" out there as well.  I appreciate you all- this community is nothing without you!

A couple of you have reached out and sent me private messages when you've not been able to get complete answers to your questions.  That's fine by me- if…

One of the longest standing capabilities in SoC-Encounter is its ability to partition a design- the process by which a design is broken up for hierarchical implementation.  I remember seeing "Big Chip? Go Hierarchical!" in marketing material for Silicon Perspective Corporation before I joined the company back in 2001 (Cadence acquired Silicon Perspective later that year), but it wasn't immediately obvious to me how the…

Heads-up: there is a free technical webinar next Wednesday 11/12 that goes deeper into the topic of combining formal verification with Cadence's planning & management technology to dramatically improve the throughput of proving assertions, and bug hunting in general.  In a phrase, this is a new "productivity flow" which my colleague Bin Ju previewed in her segment on formal verification technology.

If you would…

The SPB16.2 release is now available (actually, it was available on 10/31/08 from the Cadence software downloads site at - http://downloads.cadence.com/).

Over the next several weeks, I'll be writing about key new features available in this SPB16.2 release. I'd like to hear which features that you've been waiting to see are the most important and useful for your design requirements and which features you'd like us to tune…

In his article in Portable Design, John Donovan wrote:

Palladium Dynamic Power Analysis represents a methodology shift for power budgeting of electronic devices with system-level implications. With a focus on productivity improvement, DPA helps to quickly identify the average and peak power consumption of SoC designs running real software in various operational scenarios. Leveraging Palladium III’s built-in memory and…

Welcome Sharath Siddappa, the 5000th OVM World registrant! In only 10 months, the OVM has grown beyond 5000 registrants to more than 5200.  I took the opportunity to ask Sharath a few questions about his interest in the OVM and how he wants it to develop and here's what he had to say.

I have been working in Rambus Chip Technology (I) Pvt Ltd for past 2…

A few months back I blogged that OVM was "Open for Business".  A nice play on words, if I do say so myself, but is there real opportunity now that the door is open?

5200 OVM World participants.  10,000 downloads.  2100 forum posts.  200+ LinkedIn OVM Professionals.  That certainly describes an active community.  But how do we all monetize the OVM?  Yeah, its pretty obvious how Cadence will monetize it, but a few recent…

I'm excited to report that Tuesday's techtorial, covering a range of topics underneath the metric driven verification and OVM umbrellas, was a great success  (Here is the detailed agenda for reference http://www.secure-register.net/flyer.php?id=260). 

I make this claim not just because of the numbers (a 71% sign-up/attendee ratio -- much higher than the typical 50% you can expect in North America), but because this…

I feel that I must respond to the following blog published by Frank Schirrmeister. Virtual prototypes clearly have their value and their place in the SoC design flow (especially as platforms for software development) but they are hardly a substitute for hardware-assisted solutions and you need to find a way to connect them to your implementation and verification flows otherwise what you see may not be what you get.  Let…

This morning before heading to ESC it dawned on me that the park across the street from my hotel was the Boston Public Garden. Maybe it was the swans on the hotel logo, but the ironic thing is that the only way I knew about this park was by reading the book Make Way for Ducklings to my kids. I previously reported that 4 weeks ago we had a new baby girl. During the week following the birth, as my wife was recovering, I took…

Do you wish you could lock specific aspects of a DEHDL design content? Do you need to standardize on color used for parts, wires, text, etc. in a design? Do you wish designers would maintain a standard grid?

Well - all this (and more!) can be accomplished through the project .cpm file directive locking capabilities available since the SPB16.0 release. I'm writing about this since there are still some customers I interact…

I arrived safe and sound at the Embedded Systems Conference in Boston today. It's been a few years since I have attended ESC, but it all came back to me quickly, and is just as I remember it, a lot of small booths with vendors showing small boards doing something (hopefully something interesting and not something small).

The most interesting talk I attended was Virtualization for Embedded and Real-Time Systems. Virtualization…

The question of how to integrate legacy VMM VIP into OVM verification environments is an issue on the minds of many in the verification ecosystem.  Ed Sperling has written a good article on this subject.

For folks who have been tracking progress on the Accellera VIP TSC reflector, or in the meetings directly, it appears that progress is being made.  Of course, that progress is possible in part because the OVM has been available…