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[Please welcome Markus Winterholer to the Team ESL blog.  Markus is one of the founding members of the ISX R&D team and is from Tubingen, Germany.]

At the Embedded World Conference in Nuremberg, Germany I delivered a presentation with the title "Metric Driven Functional Verification of Embedded Software" which caused a lively discussion started by Assistant Professor Dr. Winfried Dulz from the University of Erlangen…

You are probably wondering what Virtuoso has to do with the SATs and The Dark Knight.

Well, first of all, it has only been in the past few years (so this, obviously isn’t something I’ve had to do!), but today's high school students now have to answer essay questions on the SAT test, in addition to the traditional verbal and math sections. This is to test their writing skills in preparation for college. Writing skills…

In my previous posts on the DVCon 2009 panel on Software As A Service, or "SaaS" as it applies to EDA, recall that the main issues that came up were:

• Security (the focus of Part 2 of this series)
• EDA applications that can clearly benefit from SaaS
• Bandwidth needs
• Configuration control
• Dealing with and/or migrating legacy flows & data

Having addressed the security issue in my last post and/or putting security aside…

Having consistency and correlation in timing analysis across the design flow is "very important" according to Freescale Semiconductor's Shruti Rakheja and Naveen Sampath Krishna in a recent Electronic Design News (EDN) article and I'm sure most of you would agree. As stated by Naveen & Krishna, having "perfect correlation" for timing from RTL to Signoff can dramatically improve design closure and cycle time which…

Last night when I was waiting for my daughter to finish orchestra rehearsal (she is a violin player in the Greater Twin Cities Youth Symphony) I was reading an article in the latest issue of Communications of the ACM with the title "Is Software Engineering Engineering?".  The article covered topics are near and dear to me both as an engineer working in a company that produces software and as a producer of software…

One of the coolest new things in Encounter 8.1 is Bus Guides. I know many of you out there have probably looked at the results of a routing job and thought, "Why didn't it route this bus all together? It's all over the place!" Well, with bus guides, you can get your busses routed exactly the way you want. Here's how to do it:

First, you need to create a net group.

    createNetGroup myNetGroup -net {DTMF_INST…

In IC package design, it is becoming increasingly necessary to change a cline’s width in a given region, whether for signal integrity reasons or to allow all necessary traces to pass through a particularly dense region. This can be done to a limited extent through the use of constraint areas, glossing, and the change command.

However, depending on the nature of the desired width change, this can be difficult to achieve…

[Welcome guest blogger Reuven Naveh of Specman R&D]

What is the “constraints from above” problem, and how is it solved by Specman today?

The answer: “constraints from above” are stimulus generation constraints which have the following properties:

• They constrain a do-not-generate field or its descendants.
• The constraint is declared not in the type in which the field is declared, but at a higher…

Anybody watching Cadence these past couple years has probably noticed how we're pretty serious about investing in making tools for low-power design.  While most of the attention in the EDA industry up to now has been on how to optimize chip power consumption while working at the RTL/gate level, that is going to change drastically this year, where Cadence's focus will extend to optimizing chip power consumption while working…

Recently, a colleague here at Cadence created the image of an ecosystem, whose existence was necessary to sustain the ability to take custom design into new realms of ever increasingly small and complex technologies.  He of course was referring to Virtuoso.

He asserted that “…that it takes a village” to create custom analog IC’s as well. A “village” or perhaps better labeled “ecosystem”, is due to the very specific design…

Many design teams that use SystemC  are in various stages of evaluating TLM 2.0 – the Open SystemC Initiative’s transaction level library designed for modeling memory-mapped buses and on-chip communication networks. The new standard  takes us one step closer to creating an ecosystem where ESL models can interoperate across the boundaries of design teams, IP providers, and tool vendors. TLM 2.0 designs are much…

Seems logical, but unfortunately, I run into customers today that grumble about their past experiences such as:

"Gosh, I wish our chip wasn't so big.  How did that happen?", says one ...

"Our memory requirements grew and grew, out of control, almost couldn't fit it", says another ...

"If I knew where we'd be today (which is not where I want to be), I wouldn't have bought that IP to begin with…

With TLM2 enabling more sophisticated SystemC IP interoperability, most of the new TLM IP models will come with TLM2 interfaces. Along the way there will continue to be some IP that use TLM1. For example, the recently contributed SystemC portion of OVM-ML uses TLM1 to be compatible with IP that is available today. This experiment (and I hope useful guide) to help you bridge the gap when mixing TLM1 and…

Another key differentiator of C-to-Silicon Compiler (CtoS) when compared to other ESL tools is its ability to make incremental changes to the generated RTL based on very small changes to the System C source code.

This capability, allows designers to make very small changes to the generated RTL and gate level netlists from a very small change to the input source code. Some of the changes that are supported by this approach…

[Team Specman welcomes AE Manager Avi Behar as our newest guest blogger]

Hi, my name is Avi Behar and for the past eight years I’ve been supporting Specman users from Allentown to Yokohama (any Specmaniacs at a location starting with "Z"?  I’m coming!).  If you are reading this and have been using Specman, my guess is that somewhere along the way you’ve had issues with controlling the order in which…

No, I am not kidding. in fact, we have planned several 'back to school' seminars throughout the nation to tell you all about the latest technology in digital implementation. If you are a current customer using SoC Encounter, then you would want to check this out. If you recently adopted the new Encounter Digital Implementation System, then you also would want to attend.

Here is a short preview of what you can expect…

In my last post on the DVCon 2009 panel on Software As A Service, or "SaaS" as it applies to EDA, recall that the main issues that came up were:

* Security
* EDA applications that can clearly benefit from SaaS
* Bandwidth needs
* Configuration control
* Dealing with and/or migrating legacy flows & data

Of these issues, the panelists uniformly reported that security is *always* the first thing that prospects ask…

This is the first of a series of Blogs to talk about how to fill out the forms for Harmonic Balance. I will include our suggested settings and some helpful hints. I will add to these over time as new things come up both from us and our customer base.

The existing Fillet application, a function of the Gloss routine, has been enhanced to support the dynamic updating of fillets on pins, vias or T-junctions. The application continues to support the interactive or Batch mode options as well as the parameters in place. The new dynamic option offers the convenience of filleting during interactive etch editing with no additional procedural steps.

The fill associated…

There have been a lot of new faces springing up in the signoff analysis market over the past few years and the trend seems to be pointing toward products that deliver quick and reasonably good timing signoff with some signal integrity analysis tacked on as an afterthought. This prompted me to ask the question: Just how important is noise analysis accuracy and quality?

To answer this question, I first…