• Analog/Custom Design Blogs

    Never miss a story from Analog/Custom Design. Subscribe for in-depth analysis and articles.

    Subscribe by email
  • More
  • Cancel
Featured

When AI Becomes Part of Your Analog Design Workflow

If you design analog or mixed-signal circuits, each silicon generation asks you to…

Corporate
• 6 min read
Virtuoso AI Studio , featured , agentic ai , IP Catalog , analog design

Virtuoso Studio IC25.1 ISR8 Now Available

Virtuoso Studio IC25.1 ISR8 production release is now available for download.

Virtuoso Release Team
• 5 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Analog Design Migration Made Easy With Migration Cockpit

Analog IP remains one of the most valuable and difficult-to-scale assets in semiconductor…

Vinod Khera
• 5 min read
featured , analog IP , Automated test bench migration , parasitic aware optimization , Front to back Analog Migration
Analog/Custom Design
Latest blogs

Virtuoso Meets Maxwell: Completing the Virtuoso RF Solution Assisted Flow

In my last blog, Getting Your Existing SiP File Into Virtuoso RF, I talked about…

• 6 min read
Layout SiP , Viltuoso MultiTech Framework , featured , Enablement GUI , VRF , Virtuoso Meets Maxwell , Virtuoso RF Solution , VMT , Allegro Package Designer Plus , Assisted Export , System Design Environment , fully assisted , SiP Layout Option , ICADVM20.1 , Assisted Flows , Assisted Import

Knowledge Booster Training Bytes - Virtuoso Visualization and Analysis XL

This blog describes how to efficiently use Virtuoso Visualization and Analysis XL…

• 4 min read
blended , blended training , ADE Explorer , Virtuoso Visualization and Analysis XL , learning , training , knowledge resource kit , Cadence training , digital badges , training bytes , Virtuoso , Cadence certified , Virtuoso Video Diary , Cadence Learning and Support portal , Custom IC Design , online training , Custom IC , ADE Assembler

Virtuosity: Custom IC Design Flow/Methodology - Circuit Physical Verification & Parasitic…

Read this blog for an overview to the Circuit physical verification and parasitic…

• 6 min read
design rule violations , Extraction , Layout versus schematic , Physical Verification System (PVS) , Virtuoso , Quantus Extraction Solution , PVS , Custom IC Design , parasitics

Start Your Engines: An Innovative and Efficient Approach to Debug Interface Elements…

This blog introduces you to an efficient way to debug interface elements or connect…

• 4 min read
connect modules , mixed signal design , featured , interface elements , AMS Designer , mixed-signal simulation , Virtuoso , SimVision-MS

Spectre Tech Tips: Introducing Spectre X EMIR Voltus-XFi

This blog describes the new capabilities in Spectre 21.1 ISR2 through which it provides…

• 3 min read
Spectre X EMIR , Voltus-Fi-XL , Virtuoso Analog Design Environment , Spectre X distributed simulation , Spectre X Simulator

Virtuoso ICADVM20.1 ISR26 and IC6.1.8 ISR26 Now Available

The ICADVM20.1 ISR26 and IC6.1.8 ISR26 production releases are now available for…

• 2 min read
Analog Design Environment , Cadence blogs , ICADVM18.1 , ADE Explorer , cadence , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso Visualization and Analysis XL , Layout EXL , Virtuoso Analog Design Environment , IC Release Blog , Custom IC Design , Custom IC , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL

Knowledge Booster Training Bytes - What Is a Parameterized Cell and What Are the…

Che

• 7 min read
Relative Object Design , PCells , Virtuoso Video Diary , Custom IC Design , Virtuoso Layout Suite , SKILL

Start Your Engines: AMS Flex – Our Next Generation Architecture Matures

An AMS Designer Flex simulation gives you the most immediate access to the latest…

• 3 min read
AMS Designer , AMSD , Start Your Engines , Mixed-Signal , AMSD Flex Mode , mixed-signal design , Cadence Community , AMS Flex

Spectre Tech Tips: Accuracy 101

In this post, we will learn about the most important parameters for the analog simulators…

• 3 min read
Analog Simulation , accuracy , analog , vabstol , Spectre , Simulators , iabstol , reltol , spectre x , Spectre X Simulator

Virtuoso Meets Maxwell: Getting Your Existing SiP File Into Virtuoso RF Solution

I have been involved in the Virtuoso RF Solution for the last four years. Most of…

• 6 min read
SiP , Enablement GUI , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Allegro Package Designer Plus , Assisted Export , System Design Environment , RF design , SiP Layout Option , Custom IC Design , Assisted Flows , Assisted Import , Allegro

Virtuosity: Reliability Analysis Report-Reliable Results Made Interactive

Read through this blog to know more about the new Reliability Report view in Virtuoso…

• 5 min read
SQLite , Stress Analysis , Analog Design Environment , ADE Explorer , Reliability Report , Virtuoso Analog Design Environment , Virtuoso , Spectre , Virtuosity , ISR21 , Virtuoso Video Diary , ICADVM20.1 , SQLite Operator , aging , ISR26 , reliability analysis , custom reliability data filter , Custom IC , IC6.1.8 , ADE Assembler

Training Insights: Three Things You Can Do Now to Sharpen Your Digital Implementation…

The three-day Virtuoso Digital Implementation online training course can get you…

• 2 min read
digital badges , training bytes , Virtuoso , Cadence Education Services , Custom IC Design

Knowledge Booster Training Bytes Blogs: Over 2 Years - Time to Look Back

Two years of knowledge booster blogs series, what happened during this time, important…

• 3 min read
Cadence training , training bytes , Cadence Education Services , Custom IC Design , Custom IC

Spectre Tech Tips: How to Improve the Spectre X Simulation Performance

Simulation performance is a critical factor in the time required for chip design…

• 5 min read
performance , ADE Explorer , performance diagnosis , Virtuoso Analog Design Environment , Spectre , Verifier Run Plan , spectre x , Spectre X Simulator , ADE Assembler , verification

Knowledge Booster Training Bytes – Interactive Short Locator (ISL) in the PVS LVS…

Check out this blog to see how you can debug shorts using Interactive Shorts Locator…

• 4 min read
Cadence Digital Badges , Cadence Blended Training , Physical Verification System (PVS) , Cadence training , training bytes , Cadence certified , Virtuoso Video Diary , Cadence Education Services , PVS , ISL , Custom IC Design

Virtuosity: Custom IC Design Flow/Methodology – Circuit Layout

Read this blog for an overview to the Circuit Layout design stage in Custom IC Design…

• 6 min read
Virtuoso Schematic Editor , Virtuoso Space-based Router , Virtuoso Placer , Layout Suite , Layout , ICADVM20.1 , Custom IC Design , Virtuoso Layout Suite EXL , Virtuoso Layout Suite , IC6.1.8 , Virtuoso Layout Suite XL

Virtuoso Meets Maxwell: Improving Manufacturability and Yield

This blog is to announce the official release of the Fillet capability. The Fillet…

• 2 min read
fillet , metal density , Virtuoso Meets Maxwell , Virtuoso RF Solution , T connections , Improving Manufacturability and Yield , Virtuoso RF , tapered traces

Spectre Tech Tips: Using the Spectre Strobe Feature

From time to time, we observe Spectre customers using the maxstep feature for applications…

• 4 min read
Fast Fourier Transform , ADE Explorer , strobe , Spectre Circuit Simulator , Virtuoso Analog Design Environment , Virtuoso IC6.1.8 , ADE Assembler

Knowledge Booster Training Bytes — Registrations Open: Enhancing Layout Productivity…

We are going to host a webinar on Virtuoso Layout Pro Training in the upcoming month…

• 4 min read
Cadence Digital Badges , Cadence Floorplanner , Virtuoso Layout Productivity , Module Generator , Cadence Design Planner , Cadence training , training bytes , Cadence Education Services , Custom IC Design

Virtuosity: Custom IC Design Flow/Methodology – Schematic Capture and Circuit Si…

Read this blog for an introduction to the Custom IC Design methodology and the key…

• 5 min read
Virtuoso Schematic Editor , Analog Design Environment , custom/analog , ADE Explorer , Explorer , Analog Simulation , analog , Virtuoso Visualization and Analysis XL , ADE , Virtuoso Analog Design Environment , Spectre , Schematic Editor , ViVA , Virtuosity , ICADVM20.1 , AMS simulation , mixed signal , analog design , usability , Custom IC Design , Custom IC , IC6.1.8 , Assembler , Schematic , custom design technology , ADE Assembler

Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 13: Analog Fault S…

While the analog and mixed-signal components are the leading source of test escapes…

• 4 min read
Automotive , legato , ICADVM20 , functional safety , analog fault simulation , analog , training bytes , Virtuoso , Analog IC Design videos , Spectre , 1 , Virtuoso Video Diary , aging , Custom IC Design , IC6.1.8 , reliability , Legato Reliability , ADE Assembler

Spectre Tech Tips: Using DSPF Post-Layout Netlists in Spectre Circuit Simulator

DSPF files are an integral part of post-layout simulations. This blog introduces…

• 5 min read
spectre aps , post-layout simulation , EMIR Analysis , EMIR Simulation , DSPF , netlist , Spectre , Spectre X Simulator , EMIR

Virtuoso ICADVM20.1 ISR24 and IC6.1.8 ISR24 Now Available

The ICADVM20.1 ISR24 and IC6.1.8 ISR24 production releases are now available for…

• 2 min read
Analog Design Environment , Cadence blogs , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso Visualization and Analysis XL , Virtuoso RF , Layout EXL , Virtuoso Analog Design Environment , Virtuoso , ICADVM20.1 , IC Release Blog , Virtuoso ADE Explorer , Virtuoso Layout Suite , Custom IC , Virtuoso ADE Assembler , IC6.1.8

Virtuosity: Virtuoso-Innovus Interoperability — Making Trim Shapes Interoperable

Make your Virtuoso designs Innovus ready by ensuring trim and metal shapes follow…

• 4 min read
Analog Digital Designs , Mixed-Signal Designs , Trim Shapes , Virtuoso , Virtuoso Innovus Interoperability , Virtuosity , Innovus , ICADVM20.1 , leConvertTrimmedShapesToPRStyle , leReportTrimmedShapesInCustomStyle , Custom IC Design , Interoperable IC Designs , Virtuoso Layout Suite

Virtuoso Meets Maxwell: Custom Passive Devices in RF Circuits - Devices or Interconnects…

Virtuoso Electromagnetic Solver integration allows layered parasitic extraction and…

• 6 min read
S-parameter , Extraction , Smart View , Layout versus schematic , pegusas , RFIC , parasitic , LVS , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Electromagnetic Solver , Electromagnetic analysis , EMX , Quantus Extraction Solution , graybox , ICADVM20.1 , blackbox , Quantus , Custom IC Design , EMX Solver , VMM

Spectre Tech Tips: Moving to Spectre 21.1

We deliver one major Spectre ® circuit simulator release per calendar year. The base…

• 1 min read
Spectre 21.1 , Analog Simulation

Virtuoso Meets Maxwell: Virtuoso RF Compliance Audit Smoothens Die Export

The audit functionality is a checker utility that reports all errors or warnings…

• 4 min read
Die Audit , IO Check , die export , Terms Check , Virtuoso Meets Maxwell , IC Symbol Check , Annotation Browser , Virtuoso RF Solution , Export Die , Virtuoso RF , compliance , Library Check , audit , ICADVM20.1 , Custom IC Design , VMM

Virtuoso ICADVM20.1 ISR23 and IC6.1.8 ISR23 Now Available

The ICADVM20.1 ISR23 and IC6.1.8 ISR23 production releases are now available for…

• 2 min read
Analog Design Environment , Cadence blogs , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso RF , Layout EXL , Virtuoso Analog Design Environment , Virtuoso , ICADVM20.1 , IC Release Blog , Virtuoso Layout Suite , Custom IC , IC6.1.8 , Floorplanner , Allegro , ADE Assembler
Blog - Title