Featured

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

Sean Kobayashi
• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

David Stratman
• 5 min read
conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML
Digital Design

Latest blogs

Voltus Voice: ESD Analysis Task Assistant: Your Key to 'Getting Started'

This blog discusses the implementation of task assistant for the Voltus ESD analysis…

• 4 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , ESD reports , Power Signoff , electrostatic discharge , current density , Power Integrity , ESD

Voltus Voice: Hierarchical Power Integrity Analysis—Everything You Need to Know About…

In part 2 of our "Hierarchical Power Integrity Analysis" blog series, we discuss…

• 5 min read
Voltus XM , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , xPGV models , Power Integrity , hierarchical power integrity analysis , IRdrop , Extreme Modeling , Full-Chip

Voltus Voice: 6 Tips to Jump-start Your Voltus Stylus Migration Journey

Cadence Stylus UI streamlines the RTL-to-Signoff design flow, bringing all the Cadence…

• 5 min read
Voltus IC Power Integrity Solution , Tempus , Signoff Analysis , Digital Implementation , Innovus , stylus

Do you want to Flaunt your Expertise? Grab the Digital Badge Today!

When you achieve the credit for proficiency, do you want to show it to the world…

• 1 min read
Genus , exam , badge , Joules , Synthesis

Voltus Voice: Hierarchical Power Integrity Analysis—The Quest for Accelerating Power…

To help you tackle contemporary challenges related to extremely large design power…

• 4 min read
Voltus XM , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , xPGV models , Power Integrity , hierarchical power integrity analysis , IR drop , Extreme Modeling , Full-Chip

Pegasus: Get your Wings: Pegasus Results Viewer

You will agree with me that the earlier the bugs are caught the better it is for…

• 4 min read
Pegasus Verification System , Pegasus RV , Pegasus Results Viewer , pegasus , Pegasus DRC RV

Glitch?? Do Not Let It Impact Your Design Power!!

A glitch, although, is an unnecessary signal transition in your design. But its impact…

• 1 min read
Low Power , RTL , Joules , glitch , Power Analysis , power optimization

Conformal Low Power Verification

Learn to verify low-power designs using Conformal ® Low-Power Verification. We've…

FormerMember • less than a min read

Voltus Voice: Full-Chip Resistance Analysis – The Holy Grail of Power Grid Verif…

Do you want to determine the weak spots in your power grid network at the start of…

• 6 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , power grid , Least-Resistive Path , Power Integrity , resistance analysis , IR drop , Full-Chip

Three Quick Ways to Get Up to Speed with Innovus 21.1 with Stylus Common UI

Hello Digital Designers, Innovus 21.1 released a few weeks ago and you might be…

• 1 min read
place and route , Digital Implementation , Innovus

Pegasus: Get your Wings: Pegasus Run Controls

Have you ever been in a situation where the run has started and you realize that…

• 4 min read
Pegasus Verification System , Run Control Commands , pegasus , Pegasus Run Control , signoff

Voltus Voice: Unleashing the Power of Intelligent System Design Strategy - A chat…

In this blog, Rajat Chaudhry (Product Management Director of Voltus) tells us how…

• 9 min read
Innovus Power Integrity , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , hierarchical power integrity analysis , Digital Implementation , Multiphysics System Analysis , Tempus Power Integrity

Have You Encountered Any Error/Warning During Scan Insertion in Genus? Do You Want…

Design for Test (DFT) techniques provide measures to test the manufactured device…

• 1 min read
scan , DFT , Genus , warning , error

A Proven Way to Simulate High-Frequency Electro-Magnetic Effects Using Quantus Extraction…

Cadence offers multiple electromagnetic (EM) extraction technologies to model the…

• 3 min read
Extraction , quantus rlck , Quantus

Voltus Voice: Demystifying ESD—Charting Your Way through Voltus ESD Reports

In the concluding blog of our "Demystifying ESD" series, we walk you through the…

• 6 min read
Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , ESD reports , electrostatic discharge , current density , Power Integrity , Innovus , clamp , bump

SSV 21.1 Base Release Now Available

The Silicon Signoff and Verification (SSV) 21.1 release is now available for download…

• 3 min read
Celsius Thermal Solver , Temperature Map , Voltus IC Power Integrity Solution , 3nm , Power Integrity , Power Targets , silicon signoff , Tempus Timing Signoff Solution , Extreme Modeling

Do You Know DFT Violations Can Be Debugged Using Genus GUI? Excited to Explore?

Design for Test (DFT) techniques provide measures to comprehensively test the manufactured…

• less than a min read
scan , DFT , Genus , gui , debug , Digital Implementation , Violations , Synthesis

What’s Inside the GUI-Based Timing Report in Genus? Want to Explore?

Timing closure is one of the most crucial steps of a digital design. Therefore, to…

• 1 min read
report , Genus , gui , timing debug , Timing Optimization , debug report , Synthesis

Pegasus: Get Your Wings: Strong Immunity Makes Pegasus Fault Tolerant

We all know the importance of good immunity and how a good immune system makes you…

• 1 min read
Pegasus Verification System , Fault Tolerance , pegasus , signoff , silicon signoff

Low-Power Implementation Training Videos

This blog post describes the Low Power Implementation Flow and IEEE 1801 basic terminologies…

• 1 min read
Low Power , Digital Implementation , Innovus , Power Analysis

Voltus Voice: Demystifying ESD — 5 Types of Checks to Bump up Your ESD Protectio…

This blog discusses the different Voltus electrostatic discharge (ESD) checks in…

• 4 min read
effective resistance , Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , Power Signoff , electrostatic discharge , current density , Power Integrity , Full-Chip , ESD

Verifying Design Changes Does Not Have to be Difficult and Tedious — Make it Easier…

You put your design through a multitude of tools for various transformations. Going…

FormerMember • less than a min read
conformal , formal , Logic Design , Equivalence Checking , Digital Implementation , verification

Library Characterization Tidbits: Define Measurements to Suit Your Characterization…

Do you have a requirement to specify measurements that are not default while performing…

• 3 min read
memory characterization , define_measure , Liberate MX , Library Characterization Tidbit , Liberate Characterization Portfolio

Pegasus: Get Your Wings: Virtuoso/Pegasus In-Design Signoff

The beauty of Pegasus is that it doesn’t only work excellently in standalone mode…

• 2 min read
Pegasus Verification System , Interactive SignOff Fill , pegasus , Pegasus Interactive , Density analysis , design for manufacturing

iSpatial: Next-Generation Common Physical Optimization Flow

With advanced-process nodes, a standard cell's physical delay, net delay, and congestion…

• 1 min read
Genus , Logic Design , Synthesis , ispatial , physical implementation

Voltus Voice: Demystifying ESD — Four Simple Steps to Run ESD Analysis Full-Chip…

This blog post outlines four simple steps for analysis of your electrostatic discharge…

• 5 min read
effective resistance , Silicon Signoff and Verification , Power Signoff , electrostatic discharge , current density , Power Integrity , Voltus , Full-Chip , ESD

Library Characterization Tidbits: Importance of Noise Analysis and the Role that…

The hustle bustle of the cities is only an example of the external noise, which we…

• 5 min read
CCSN characterization , CCSN , Liberty Variation Format , Reference-based modeling , cross coupled capacitance , characterization , composite current source noise , noise in digital circuit , CCS Noise , Library Characterization Tidbit , channel connected blocks , coupling cap , Liberate , noise propagation , Liberate Characterization Portfolio , Stage-based modeling , CCB , timing

Understanding Clock Gating Report and Cells

Hi everyone, Are you interested in reducing the power dissipation of your design…

• 2 min read
digital badge , blended training , Genus , training bytes , Digital Implementation , online training , cadence learning and support
Blog - Title