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Custom IC Design

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  • Discussion

    Problem in doing pss pnoise simulation to get PFD CP output current noise

    Category: Custom IC Design

    By macanfeng11 macanfeng11

    •

    updated over 4 years ago by Andrew Beckett

    6 replies • 15120 views
  • Discussion

    How to mark a floating bus net as noConn in Schematic Composer in IC5141

    Category: Custom IC Design

    By RFStuff RFStuff

    •

    updated over 4 years ago by Andrew Beckett

    6 replies • 20743 views
  • Discussion

    Techgen Error: Starting Triangle not defined

    Category: Custom IC Design

    By CasV CasV

    •

    updated over 4 years ago by CasV

    4 replies • 12141 views
  • Discussion

    The Principle of Automatic Sweeping

    Category: Custom IC Design

    By Matsuge Matsuge

    •

    updated over 4 years ago by Matsuge

    4 replies • 13960 views
  • Discussion

    Convergence issue with Verilog-A model

    Category: Custom IC Design

    By AQoutb AQoutb

    •

    updated over 4 years ago by Andrew Beckett

    4 replies • 15435 views
  • Discussion

    Variable set in corners overrides variable locally defined in test

    Category: Custom IC Design

    By SteveDobbs SteveDobbs

    •

    updated over 4 years ago by Andrew Beckett

    4 replies • 12608 views
  • Discussion

    Virtuoso schematic set net to default to a certain color

    Category: Custom IC Design

    By CSCNalu CSCNalu

    •

    updated over 4 years ago by Andrew Beckett

    3 replies • 13644 views
  • Discussion

    Analysis was skipped due to inability to compute operating point.

    Category: Custom IC Design

    By AQoutb AQoutb

    •

    updated over 4 years ago by Andrew Beckett

    3 replies • 16468 views
  • Discussion

    trouble with auto routing minimum spanning tree, Layout XL

    Category: Custom IC Design

    By helloIamAndrea helloIamAndrea

    •

    started over 4 years ago

    0 replies • 11155 views
  • Discussion

    Problem in simulating an inverter using BSIMCMG

    Category: Custom IC Design

    By Engto Engto

    •

    updated over 4 years ago by Andrew Beckett

    1 replies • 11395 views
  • Discussion

    How to ignore FILL cells from Encounter in LVS Assura?

    Category: Custom IC Design

    By Kabal Kabal

    •

    updated over 4 years ago by RobMan

    6 replies • 17728 views
  • Discussion

    ERROR EMX in virtuoso

    Category: Custom IC Design

    By tawsaras tawsaras

    •

    updated over 4 years ago by Andrew Beckett

    6 replies • 15497 views
  • Discussion

    [AWR Microwave Office] Issue related to plot of contours

    Category: Custom IC Design

    By Eres Eres

    •

    started over 4 years ago

    0 replies • 11766 views
  • Discussion

    *ERROR* (AMS-1245): AMS UNL netlisting" in AMS simulation

    Category: Custom IC Design

    By RFStuff RFStuff

    •

    updated over 4 years ago by Andrew Beckett

    3 replies • 4143 views
  • Discussion

    Plotting a Graph in cadence with different axis variables DC-Analysis Design variable

    Category: Custom IC Design

    By mirtaji65 mirtaji65

    •

    updated over 4 years ago by Andrew Beckett

    1 replies • 18290 views
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