Logic Design

Latest Posts

Discussion

RTL Compiler functions with regexp

Category: Logic Design

By menime54
•
updated over 9 years ago by grasshopper

3 replies • 14809 views
Discussion

RTL Compiler command questions: pwd, multicore options, and program name

Category: Logic Design

By menime54
•
updated over 9 years ago by grasshopper

1 replies • 14897 views
Discussion

What is the usage of memory library from the PDK?

Category: Logic Design

By dogrush
•
updated over 9 years ago by grasshopper

1 replies • 13554 views
Discussion

Not mapped points in LEC when using DC netlist

Category: Logic Design

By Adi Mashiah
•
started over 9 years ago

0 replies • 13585 views
Discussion

check clock_gating gives 0 gated flip-flops after synthesize

Category: Logic Design

By zczc99
•
updated over 9 years ago by grasshopper

3 replies • 15058 views
Discussion

clock gating timing report with synthesized ICG cell

Category: Logic Design

By zczc99
•
started over 9 years ago

0 replies • 16419 views
Discussion

RC Physical Flow - Spare Module

Category: Logic Design

By Yemelya
•
updated over 9 years ago by grasshopper

1 replies • 1020 views
Discussion

do I need to use write_hdl -lec for equivalence check ?

Category: Logic Design

By zczc99
•
updated over 9 years ago by grasshopper

1 replies • 1240 views
Discussion

How to connect a common test port to all the CG cells for clock gating?

Category: Logic Design

By zczc99
•
updated over 9 years ago by grasshopper

1 replies • 13809 views
Discussion

Low power flow. State retention problem.

Category: Logic Design

By tfanni
•
started over 9 years ago

0 replies • 13113 views
Discussion

RTL Compiler synthesis with inference to a custom cell

Category: Logic Design

By jjgs
•
updated over 10 years ago by grasshopper

1 replies • 14449 views
Discussion

LEC - MOS direction and abstract logic error

Category: Logic Design

By sacmax
•
started over 10 years ago

0 replies • 943 views
Discussion

Multiplier Selection in RTL compiler

Category: Logic Design

By AliShami
•
updated over 10 years ago by leapfrog

2 replies • 15107 views
Discussion

Conformal LEC hier_compare only on 1 module

Category: Logic Design

By Matt Hutson
•
updated over 10 years ago by Matt Hutson

2 replies • 16285 views
Discussion

Find the dynamic power from incisive which depends on the testbench

Category: Logic Design

By raja92
•
updated over 10 years ago by grasshopper

1 replies • 13272 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.