• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      JCTEYSSIER0
      JCTEYSSIER0 85 Points
    • 2
      oldmouldy
      oldmouldy 70 Points
    • 3
      ltoohey
      ltoohey 65 Points
    • 4
      Hoangkhoipcb
      Hoangkhoipcb 50 Points
    • 4
      MD202602226914
      MD202602226914 50 Points
  • Leaderboard

    • 1
      steve
      steve 17,774 Points
    • 2
      oldmouldy
      oldmouldy 13,775 Points
    • 3
      eDave
      eDave 10,331 Points
    • 4
      ShawnLogan
      ShawnLogan 9,720 Points
    • 5
      skillUser
      skillUser 7,518 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    tie cell net connection missing

    Category: Digital Implementation

    By iamravikiran

    •

    started over 8 years ago

    0 replies • 13894 views
  • Discussion

    What's the problem of my custom PCB design using a CC1310 radio?

    Category: PCB Design

    By Menege

    •

    started over 8 years ago

    0 replies • 1735 views
  • Discussion

    ncelab and ncvlog version error conflict

    Category: Functional Verification

    By mhkvy4

    •

    updated over 8 years ago by Adwaya

    4 replies • 19754 views
  • Discussion

    How to open Cadence 6.15 using AMS CMOS 0.35um design kit

    Category: Custom IC Design

    By UUinfini

    •

    updated over 8 years ago by uschi

    1 replies • 14601 views
  • Discussion

    irun elaboration issue: vhdl package with relative path not found

    Category: Mixed-Signal Design

    By dani0815

    •

    started over 8 years ago

    0 replies • 15801 views
  • Discussion

    Conditional Expression in Design Variable in AMS

    Category: Mixed-Signal Design

    By twen

    •

    updated over 8 years ago by Andrew Beckett

    3 replies • 19413 views
  • Discussion

    Using Split Parts - Allegro Design Entry HDL 16.6

    Category: PCB Design

    By gray88

    •

    updated over 8 years ago by steve

    1 replies • 2847 views
  • Discussion

    I/O pad pins are placed randomly (each pad_pin is not placed on the corresponding pad)

    Category: Digital Implementation

    By Andorra

    •

    started over 8 years ago

    0 replies • 1309 views
  • Discussion

    Simulation CPU cores usage

    Category: Mixed-Signal Design

    By AllenD

    •

    updated over 8 years ago by Andrew Beckett

    3 replies • 22002 views
  • Discussion

    Body Connection for 18nm process finfet

    Category: Custom IC Design

    By myjan

    •

    updated over 8 years ago by Andrew Beckett

    1 replies • 14725 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information