• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      eDave
      eDave 60 Points
    • 2
      MZ20250602835
      MZ20250602835 51 Points
    • 3
      Aurel B
      Aurel B 41 Points
    • 4
      steve
      steve 40 Points
    • 4
      ShawnLogan
      ShawnLogan 40 Points
  • Leaderboard

    • 1
      steve
      steve 17,769 Points
    • 2
      oldmouldy
      oldmouldy 13,705 Points
    • 3
      eDave
      eDave 10,331 Points
    • 4
      ShawnLogan
      ShawnLogan 9,710 Points
    • 5
      skillUser
      skillUser 7,498 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    Why is Spectre ignoring time tolerance or time step conditions from Verilog-AMS models?

    Category: Custom IC Design

    By DomiHammerfall

    •

    updated over 1 year ago by DomiHammerfall

    2 replies • 6411 views
  • Suggested Answer

    Nets in the PCB layout not respecting the spacing rules provided in the constraint manager

    Category: Allegro X PCB Editor

    By RohitRohan

    •

    updated over 1 year ago by RohitRohan

    13 replies • 9971 views
  • Discussion

    how to force the variables inside a class? i'm facing this error "FOAUTO"

    Category: Functional Verification

    By chetan somana

    •

    updated over 1 year ago by chetan somana

    6 replies • 4762 views
  • Answered

    shape splits

    Category: Allegro X PCB Editor

    By masamasa

    •

    updated over 1 year ago by masamasa

    6 replies • 7851 views
  • Discussion

    Tagging uvm_errors in waveform file for post-processing

    Category: Functional Verification

    By antmarzam

    •

    updated over 1 year ago by Doug Koslow

    3 replies • 6446 views
  • Answered

    Net alias label deleted by mistake, howto get it back

    Category: Allegro X Capture CIS

    By luqa

    •

    updated over 1 year ago by luqa

    4 replies • 4443 views
  • Discussion

    Using environment variables in Model Libraries form

    Category: Custom IC Design

    By mazorra

    •

    updated over 1 year ago by mazorra

    4 replies • 7351 views
  • Discussion

    What’s new in Celsius Thermal Solver 2023.1 HF2 - #1

    Category: Celsius Thermal Solver

    By SimTech

    •

    started over 1 year ago

    0 replies • 1073 views
  • Answered

    Unable to modify or delete the nested net group present in the Constraint

    Category: Allegro X PCB Editor

    By JITHINDEV

    •

    updated over 1 year ago by jc teyssier

    4 replies • 6717 views
  • Discussion

    system() function is executed before other instructions.

    Category: Custom IC SKILL

    By LoVyacheslavvVEMs

    •

    updated over 1 year ago by LoVyacheslavvVEMs

    2 replies • 5440 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information