• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      ltoohey
      ltoohey 66 Points
    • 2
      MZ20250602835
      MZ20250602835 62 Points
    • 3
      oldmouldy
      oldmouldy 55 Points
    • 4
      steve
      steve 45 Points
    • 4
      JCTEYSSIER0
      JCTEYSSIER0 45 Points
  • Leaderboard

    • 1
      steve
      steve 17,774 Points
    • 2
      oldmouldy
      oldmouldy 13,740 Points
    • 3
      eDave
      eDave 10,331 Points
    • 4
      ShawnLogan
      ShawnLogan 9,710 Points
    • 5
      skillUser
      skillUser 7,508 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    How to connect a via in few GND layers while disconnecting it on remaining GND layers

    Category: PCB Design

    By Khurram

    •

    updated over 12 years ago by redwire

    2 replies • 15631 views
  • Discussion

    How to setup DRC to allow package overlap?

    Category: PCB Design

    By Leeya

    •

    updated over 12 years ago by Robert Finley

    1 replies • 14644 views
  • Discussion

    SimCompare - ignore time - compare only values

    Category: Functional Verification

    By GiuseppeDG

    •

    started over 12 years ago

    0 replies • 788 views
  • Discussion

    saving ams config hierarchy

    Category: Mixed-Signal Design

    By kawan

    •

    updated over 12 years ago by kawan

    2 replies • 14909 views
  • Discussion

    how to use skill function to create layout library with virtuoso tf file

    Category: Custom IC SKILL

    By tomchen

    •

    updated over 12 years ago by tomchen

    2 replies • 17357 views
  • Discussion

    STB analysis stops running ... with no error in output.log

    Category: Custom IC Design

    By Praveen K

    •

    updated over 12 years ago by Praveen K

    2 replies • 15690 views
  • Discussion

    Issue creating VIAs in SKILL

    Category: Custom IC SKILL

    By egolowen

    •

    updated over 12 years ago by Andrew Beckett

    1 replies • 13944 views
  • Discussion

    VerifyGeometry not parsing all the sub area

    Category: Digital Implementation

    By AnandThibbaiah

    •

    updated over 12 years ago by wally1

    3 replies • 14726 views
  • Discussion

    Parameters and pcells in ADE XL

    Category: Custom IC SKILL

    By kvntien

    •

    updated over 12 years ago by kvntien

    4 replies • 15966 views
  • Discussion

    How to put the Multilayer board in Layout 16

    Category: PCB Design

    By Dhamodharann

    •

    updated over 12 years ago by Dhamodharann

    2 replies • 13417 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information