• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      masamasa
      masamasa 129 Points
    • 2
      excellon1
      excellon1 127 Points
    • 3
      steve
      steve 100 Points
    • 4
      DavidJHutchins
      DavidJHutchins 90 Points
    • 5
      avant
      avant 76 Points
  • Leaderboard

    • 1
      steve
      steve 17,699 Points
    • 2
      oldmouldy
      oldmouldy 13,625 Points
    • 3
      eDave
      eDave 10,251 Points
    • 4
      ShawnLogan
      ShawnLogan 9,660 Points
    • 5
      skillUser
      skillUser 7,617 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    Input referred sampled pnoise

    Category: Custom IC Design

    By Matthew Love

    •

    updated over 1 year ago by ShawnLogan

    3 replies • 6181 views
  • Suggested Answer

    Orcad Capture: Keep the references and delete the underlined

    Category: Allegro X Capture CIS

    By calinixta

    •

    updated over 1 year ago by calinixta

    3 replies • 6559 views
  • Discussion

    EMX parametric simulations of a PCELL

    Category: RF Design

    By ArbLouis

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 5960 views
  • Answered

    how add custom menu callback with OrCAD_Capture.xml or capTCLMenu.tcl?

    Category: Allegro X Capture CIS

    By kwxsp86

    •

    updated over 1 year ago by kwxsp86

    5 replies • 5676 views
  • Discussion

    Aligning Components using Offset Mode in Allegro X APD

    Category: Allegro X APD

    By PCBTech

    •

    started over 1 year ago

    0 replies • 5712 views
  • Discussion

    Error using cds_innersrr

    Category: Custom IC Design

    By elic253

    •

    updated over 1 year ago by elic253

    4 replies • 6007 views
  • Discussion

    [Solved]Cannot open layout view due to stuck at "tsmcCdfFormInitCB"

    Category: Custom IC Design

    By yuh wang

    •

    started over 1 year ago

    0 replies • 1513 views
  • Discussion

    how to see value of Verilog variable in ams batch mode simulation?

    Category: Mixed-Signal Design

    By wangyunxin

    •

    updated over 1 year ago by tpylant

    1 replies • 8579 views
  • Not Answered

    simulation failed

    Category: PSpice

    By Jamshid1995

    •

    updated over 1 year ago by AyushD

    1 replies • 4519 views
  • Discussion

    Change default plot setting (log-scale & line plot)

    Category: Custom IC Design

    By ashwinrs

    •

    updated over 1 year ago by Andrew Beckett

    1 replies • 2034 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information