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The full agenda for CDNLive Boston is now available. This is really "East Coast" CDNLive since it is the only CDNLive in the US outside of Silicon Valley. I've not been before, but I understand that people from places like Atlanta and Florida attend,...

If you live in the US, then it is hard to believe how dominant Nokia was in mobile. For a time, one in every three mobile phones sold was a Nokia. But they were never a major force in the US for various reasons. But they built a million phones a day back...

New Model Management capabilities are now available in the SPB 16.6 Allegro Design Workbench (ADW) release.

The new model management capability involves creating an environment that manages new model types for the PCB Librarian and other model editors. The benefits:

• Enhance the 16.6 SI DM Model flow for ease of use
• Create a new generic adapter to support a file system based model type
• Create a new generic model…

When using the Add Connect command in the 16.6 Allegro PCB Editor, the active layer field will now automatically synchronize to that of a single visible layer. Previously, any visibility adjustment to limit the display to a single etch layer would typically require an additional adjustment to the active layer setting.

Invoke the ‘Add Connect’ command. Disable the visibility of all etch layers:

Enable the…

By default, the top and bottom stackup layers do not support the placement of embedded components. When an attempt is made to change ‘Embedded Status’ to either ‘Body up’ or ‘Body down’, the system will prompt you accordingly. To help facilitate the requirement for placing components between the top and bottom layers, the 16.6 Allegro PCB Editor release now supports the placing of components…

Applying a weighting factor to a Noise Summary run requires lots of steps and the results cannot be evaluated without using the form. Wouldn't it be much easier if you could have a calculator function to do this?

You can create a custom function in the calculator that uses the script attached, weightedTotalNoise.il, simplifying this flow.

In order to apply a weighting factor to a Noise Summary…

Hey, did you hear the buzz around the new Virtuoso ADE product suite, which was introduced in IC6.1.7? The products in this suite—Virtuoso ADE Explorer, Virtuoso ADE Assembler, and Virtuoso ADE Verifier—have made a good start, just as we expected!

The new single-test simulation environment, Virtuoso ADE Explorer, provides some really exciting features. Our favorite ones are real-time tuning with Spectre,…

For nearly all applications, customers continue to demand smaller, lighter, and more cost-effective products. Competitive pressures also force designers to bring these new products to market at an ever-increasing rate. Designers can deploy flexible PCB materials (flex/rigid-flex) to meet challenging form-factor requirements, eliminate connectors, and improve performance.

It might seem a bit premature to be talking about IEDM since it isn't until December. But the deadline for submissions has been extended this year to August 10 (so still just a couple of weeks away). Why? As this year's publicity chair, Martin Giles,...

Today at the Linley Mobile and Wearables Conference in Santa Clara, Cadence is announcing the latest Tensilica DSP. The Tensilica^® Fusion G3 is a multi-purpose low-power DSP targeted at mobile and other markets. Usually when we design a new processor...

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In this week's Whiteboard Wednesdays video, Paul Garden provides an introduction to the new Tensilica Fusion G3 DSP for automotive, mobile, industrial, and general embedded DSP applications. He’ll discuss the main features of the Fusion G3 DSP, highlight some of the target applications, and provide a quick overview of some of the key software deliverables. The Fusion G3 is a multi-purpose fixed- and floating-point DSP…

One of the most interesting sessions that I attended at SEMICON West the week before last was titled Pathfinding Beyond 5nm. This was moderated by David Hemker, the CTO of Lam Research.

An Steegen, imec

The first speaker was An Steegen of imec. She...

CDNLive India is coming up on August 9th and 10th in Bengaluru. I will be there and so Breakfast Bytes will be covering some of what goes on there. It is not my first trip to India or even to Bengaluru (although it was still called Bangalore back then...

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You can access product manuals for all the supported releases. Have you checked out Sigrity 2016 documents yet? If not, click here ……

PSpice.com is a new user-community web portal that lets designers, partners, and students access materials related to PSpice® analog and mixed-signal simulation and analysis in one central location.

“The PSpice web portal and community is a good resource for any analog or mixed-signal engineer creating an electronic design,” said Makram Mansour, Ph.D., WEBENCH Manager at Texas Instruments. “Within the www.PSpice…

With DAC and other events during May and June, I am only now wrapping up stuff I wanted to write about from EDPS in Monterey. Cadence's T.C.Lin presented about the importance of system-level power and ended up with a recipe of how to do it.

I won...

The Allegro 17.2-2016 release, the largest in the past 10 years, became available in late April 2016. Since 17.2-2016 includes a database change that usually happens with a dot zero release, many of you may be wondering when the right time to migrate to this new release is.

Included below is an overview of the Top 10 reasons to move up to the Allegro 17.2-2016 release, so that you can better understand the value of each…

Modern fabs use 300mm (12") wafers. Older fabs have used 200mm (8") wafers since the early '90s, starting with IBM Fishkill's pilot with Siemens to build 64Mb DRAM in 1990. Before that, we had 5" wafers (150mm), and if you go back far enough in history...

Growing deployment level of 10 Gigabit Ethernet in datacenters and automotive infotainment is driving the demand and the connectivity needs of a broad range of high-end, energy-efficient networking and computing applications.

Energy-efficient networking in server area basically means elimination of packet loss, server virtualization with support for several applications and operating systems on a server; all by defining…

My docking station with the rat’s nest of wires dangling from behind it could be going the way of the Dodo bird soon, thanks to USB Power Delivery (PD) protocols and USB Type-C connectors.

The traditional docking station that we all know and hate, typically looks something like the picture below.

This is a photo of my docking station at work. These docking stations have 3 main problems:

1. There is a mess of…

With the 16.6-2015 Allegro PCB Editor release, the Snake pattern router can be enabled from the context menu of the Add Connect command. This functionality provides the ability to route through hex pattern packages utilizing arc routing, which has been greatly improved compared to the existing prototype pattern generator. Simply enable Snake mode via the RMB and Add Connect will detect a hex pattern pin/via field and…

The Monday before SEMICON West starts, there are two events that run in parallel in the Marriott Hotel. One is imec's US technology forum. Since I already attended the two-day version in Brussels, and wrote about it over the last couple of months, I attended...

Cadence was awarded with the IEEE Donald O. Pederson Best Paper Award—EDA’s most prestigious recognition of its kind—for the best paper published in IEEE Transactions on CAD over the past two years. 

The paper, “Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space”, was part of a collaboration with Carnegie Mellon University.…