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Latest Blog Posts

  • Academic Network: What Was on Offer at European Test Symposium (ETS) 2016 in Amsterdam?

    ChristinaB
    ChristinaB

    CAN_logoIEEE European Test Symposium (ETS) is the largest event in Europe committed to presenting and discussing scientific trends, emerging results, hot topics and applications in the area of electronic-based circuits and system testing. ETS’16 which took place...

    • 21 Jun 2016
  • Academic Network: Students From Tianjin University in China Visit Cadence Sophia

    susarla
    susarla

     Back in May, Professor Gilles Jacquemod and 9  engineering students from Tianjin University who are currently visiting Sophia-Antipolis engineering school stopped by the Cadence office in Sophia, France.The students have been selected to participate in...

    • 21 Jun 2016
  • Breakfast Bytes: Gary Patton: What's Next? Markets and Technology

    Paul McLellan
    Paul McLellan

     gary pattonOne of the keynotes at the imec technology forum last month was by Gary Patton, the CTO of GLOBALFOUNDRIES. I reminded him in the evening event at the Magritte museum that he'd done an interview with me last year that had gone viral inside GLOBALFOUNDRIES...

    • 21 Jun 2016
  • SoC and IP: Can You See Me? Putting Neural Networks in Everyday Devices

    IPGuy
    IPGuy

     Neural networks have become very popular today due to their use in leading-edge technology like deep learning machines, artificial intelligence, and virtual reality. Neural networks offer a powerful way to extract meaning in recognizing objects and actions within a visual stream. It's a topic with a lot of buzz today, and as the use of it becomes more and more pervasive, it’s just a matter of time before the devices we…

    • 20 Jun 2016
  • SoC and IP: The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016

    Steve Brown
    Steve Brown

    PCI-SIG is a leading event in cloud infrastructure transformation, which is markets all over the world. We see a lot of market forces at work, creating urgency for PCIe Gen4 dynamics. Designers, system architects, engineers and engineering managers will be the driving force behind another PCI-SIG event. Taking place on June 28-29 2016 at the Santa Clara Convention Center, California, this prestigious event is filled with…

    • 20 Jun 2016
  • Academic Network: CDNLive EMEA: An Intern's Perspective

    ChristinaB
    ChristinaB

    CANCDNLive EMEA is often cited as the most exciting event of the year for Cadence. This being the first time I would be attending any CDNLive, I was eager to see for myself if this was true and I must say in retrospect, that all my expectations were met...

    • 20 Jun 2016
  • Breakfast Bytes: 99.7% of Transistors Manufactured Are Memory

    Paul McLellan
    Paul McLellan

      magritte pipe dessertI was in Brussels a couple of weeks ago to attend imec's annual technology forum. One of the keynotes on the first morning was from Wally Rhines, Mentor's CEO, entitled Extending Semiconductor Cost Reduction Another 20 Years. As Gordon Moore himself...

    • 20 Jun 2016
  • Breakfast Bytes: RISC-V—Instruction Sets Want to Be Free

    Paul McLellan
    Paul McLellan

     I had never heard of the RISC-V (pronounced five, not vee) instruction set until earlier this year when there was a presentation about it at EDPS in Monterey. I immediately texted the daughter of a friend of mine who is a CS major at Berkeley where it...

    • 19 Jun 2016
  • Verification: IP Group @ 53rd DAC – Veni Vidi Vici

    Steve Brown
    Steve Brown

    Another DAC, and this year someone put a jalapeno in my margarita at the Denali Party. The burn came on slow, and was merciless. So we all yelled “Carpe Diem!”

    The really good news is that there was a lot of traffic at the floor show, and we seemed to garner the largest crowds. Overall attendance was strong. And we saw increased interest in customers talking with our IP technical experts at the Expert Bar…

    • 17 Jun 2016
  • Analog/Custom Design: Waveform Thumbnails

    TeamADE
    TeamADE

    Wouldn't it be great if you could see your plots directly on the schematic? Well in ADE Explorer, now you can!

    Run a simulation in Explorer and open the design in tab and choose Waveforms from the show/hide balloon drop down or use the bind key CTRL+B

    Hover over the nets/terminals in the design and balloons showing the simulation plot will appear.

    To pin the balloons use the bindkey SHIFT+B or click on…

    • 17 Jun 2016
  • Academic Network: Open Source Raspberry Pi Design Files for Allegro and OrCAD Tools

    G Cochrane
    G Cochrane

    The Raspberry Pi has firmly established itself as a household name by providing a hands-on way to learn programming in a small, simple, and very affordable package. First released just over 4 years ago in February 2012, the device can not only handle...

    • 16 Jun 2016
  • Breakfast Bytes: Seamless Verification

    Paul McLellan
    Paul McLellan

     At DAC, Cadence had their now traditional verification lunch. Brian Fuller returned in his role as the host and moderator. The panel consisted of:

    • Jim Hogan of Vista Ventures, another Cadence alumnus, and an expert on the EDA industry in general (and...
    • 16 Jun 2016
  • Academic Network: Cadence Technology Days at MIET

    Anton Klotz
    Anton Klotz

    Cadence Academic Network logo

    On 21 April, Cadence and the Moscow Institute for Electronics Technologies (MIET) organized Technology Days in the MIET building in Zelenograd in the vincinity of Moscow. Zelenograd is the heart of the Russian microelectronics industry—both Russian foundries...

    • 15 Jun 2016
  • Academic Network: Visiting KAUST

    Anton Klotz
    Anton Klotz

    Cadence Academic Network logo

    Cadence Academic Network is a worldwide activity; therefore, the team members are often traveling to quite exotic places on earth to visit universities, talk with the professors, and tell them what Academic Network can offer them. One of the most...

    • 15 Jun 2016
  • System, PCB, & Package Design : What's Good About Allegro PCB Editor Fiber Weave Effect—Zig-Zag Routing? New Capabilities in 16.6-2015!

    Jerry GenPart
    Jerry GenPart

    The 16.6-2015 Allegro PCB Editor release introduces the interactive conversion of Orthogonal and 45-degree routed traces into a Zig-Zag pattern to minimize the Fiber Weave Effect in a Printed Circuit Board (PCB).

    What is “Fiber Weave Effect”?...

    • 14 Jun 2016
  • Academic Network: Academic Track at CDNLive EMEA

    G Cochrane
    G Cochrane

    CAN logoFrom May 2 to May 4, Cadence once again hosted their hugely popular user conference CDNLive EMEA. The Academic Track, co-ordinated by the Cadence Academic Network, is a platform to share papers about advances in teaching methods and research techniques...

    • 14 Jun 2016
  • SoC and IP: Compatibility Is Good, But Compliance Is Better—Certifying for VESA DisplayPort

    Jacek Duda
    Jacek Duda

    For all IP providers, the ultimate proof of quality of their product is certification for standard compliance. Exhaustive testing conducted by third-party labs or at compliance workshops assess the behavior of the component across variety of conditions that can take place in customer’s application. Passing the compliance suite helps both convince existing prospects, as well as promote to get new ones.

    Cadence has…

    • 14 Jun 2016
  • Whiteboard Wednesdays: Whiteboard Wednesdays—Vision Systems and Neural Networks

    References4U
    References4U

    In this week's Whiteboard Wednesdays video, Chris Rowen discusses using neural networks as part of vision systems.

    https://youtu.be/5vj8coVTN_4

    • 14 Jun 2016
  • Breakfast Bytes: An Steegen: Controlling the Semiconductor Funnel

    Paul McLellan
    Paul McLellan

     Last week I was in Belgium for imec's international technology forum (ITF). For me one of the high spots is always An Steegan's presentation on what is going on just over the horizon in process development. I will write about that in a week or two once...

    • 14 Jun 2016
  • Analog/Custom Design: Virtuoso Video Diary: Redesigned Virtuoso Forms

    KomalJohar
    KomalJohar

    Enhanced User Experience with Redesigned Virtuoso Forms

    Research and customer feedback has revealed that you feel some Virtuoso forms are quite complex, with too many options displayed on the forms and use models that are unclear. Based on your feedback, we have begun redesigning the most frequently used forms across Virtuoso applications.

    As you start to use the redesigned forms in Virtuoso, you will see that they are…

    • 13 Jun 2016
  • Breakfast Bytes: Securing the IoT for Billions of Possible Intrusion Points

    Paul McLellan
    Paul McLellan

    Breakfast Bytes logoTrust-Crypto-Anti-TamperAt the Linley IoT conference a few weeks ago, one of the presentations was by NXP's Donnie Garcia. As in all such presentations, there was some bias towards the best solution being an NXP microprocessor, but most of the presentation was at a higher level...

    • 13 Jun 2016
  • Breakfast Bytes: Lip-Bu's Fireside Chat with Ed Sperling—With Real Fire

    Paul McLellan
    Paul McLellan

     Usually the phrase "fireside chat" is just a figure of speech, but Wednesday's came with a real fire. A spotlight caught fire above Mentor's booth, and the entire conference center was evacuated for half an hour or so. Luckily, we got the all-clear and...

    • 10 Jun 2016
  • Breakfast Bytes: DAC News, Wednesday

    Paul McLellan
    Paul McLellan

    DAC logoThe last day of the DAC tradeshow is the best...said nobody ever. After two days in the booth for exhibitors, or two days watching non-stop demos and presentations for attendees, the third day seems endless. Although the exhibition finishes on Wednesday...

    • 9 Jun 2016
  • Breakfast Bytes: DAC News, Tuesday

    Paul McLellan
    Paul McLellan

    DAC logoironworks barbecueTuesday, the second day of DAC. Last night I learned that in Texas there is a third thing that you don't discuss, to go along with politics and religion: barbecue. After the show closed, we went to the Iron Works barbecue, which is almost around the back...

    • 8 Jun 2016
  • Analog/Custom Design: Analog Design Resonance: When a Plan Comes Together

    TeamADE
    TeamADE

    Yes, indeed, we all love it when a plan comes together. A plan for running all the simulations you need, using different combinations of tests, corners, variables, and run modes. A plan that you can execute with a single button before you go home in the evening. A plan that will stop if, for some reason, your design isn't performing to spec so that you aren't wasting resources running simulations on a bad design. The…

    • 7 Jun 2016
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