Find Other Members ►

Get email delivery of the Cadence blog (individual posts).

Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Analog/Custom Design: Virtuosity: SKILLful Virtuoso Visualization and Analysis

Ashu V

If you’re a SKILL enthusiast, you’ll be happy to know that the latest IC6.1.7 ISR release offers some very useful and handy SKILL functions to perform certain tasks in ViVA. You may find them useful too. Let’s take a quick look at them.
- 10 Dec 2017
Breakfast Bytes: IEDM 2017

Paul McLellan

The start of December means it is the International Electron Devices Meeting in San Francisco (it used to be in Washington alternate years but it is in San Francisco for the forseeable future). I have been here all week. Highlights were keynotes from...
- 8 Dec 2017
Analog/Custom Design: Virtuosity: Can I Graphically Edit Width Spacing Patterns?

KomalJohar

We have enhanced the editing modes available for WSPs. In addition to the text-based editing, you can now graphically edit WSPs in the preview mode.
- 7 Dec 2017
Academic Network: 2017 Workshop on Electronic Design Automation in Tainan Taiwan

Tracy Zhu

It was the third continuous year that Cadence Academic Network supported the Workshop on Electronic Design Automation (EDA) in Taiwan. The event was hosted by National Cheng Kung University in Tainan on December 2-3, 2017. &nb...
- 7 Dec 2017
Breakfast Bytes: Greg Yeric and Rob Aitken Dive into the Details

Paul McLellan

The last day of TechCon had two keynotes rich in deeper technical content, from Greg Yeric on Process Technology Limbo, and Rob Aitken, on How to Build and Connect a Trillion Things. Greg Yeric Greg is focused on what new technologies are going to be...
- 7 Dec 2017
Breakfast Bytes: Advanced Packaging Delivers More Than Moore

Paul McLellan

Moore's Law is running out of steam. Depending on your point of view, it is dead, dying or slowing. As a result, there is an increasing interest in technologies that go under the title "More than Moore", meaning ways of getting better ...
- 6 Dec 2017
Digital Design: Get Early Silicon Learning to Accelerate Yield Ramp-up

Philippe Hurat

How important is it for your advanced node products to get early silicon learning? How are your test chips compared to real products? Some answers are provided below in short summary from the “Methodology for Analyzing and Quantifying Des...
- 5 Dec 2017
Whiteboard Wednesdays: Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 2

References4U

In this week's Whiteboard Wednesday, Tom Hackett continues his explanation of neural network basics using an Excel spreadsheet as a learning vehicle. You can download the spreadsheet here: https://ip.cadence.com/uploads/1213/neural-network-calculator-xlxs-zip

https://youtu.be/ow1ZuOPD72I
- 5 Dec 2017
Analog/Custom Design: Virtuosity: Can I Plot Signals with Different Axis Units in the Same Window?

Arja H

Have you been frustrated trying to drag signals around in Virtuoso Visualization and Analysis only to see this icon telling you that you can't drag the signal there? You can right-click on the axis and check the Allow Any Units option,...
- 5 Dec 2017
Breakfast Bytes: Supercomputers

Paul McLellan

HPC, or high-performance computing, is one of the big focus areas for semiconductors (along with mobile, automotive and IoT). The highest performance computing of all are the supercomputers. Whereas the computers we have on our laptops, smartpho...
- 5 Dec 2017
Analog/Custom Design: Virtuosity: CDNLive India—Our Window to KYC!

Rishu Misri Jaggi

In line with the recently-implemented mandate in India requiring banks and financial institutions to regularly run “Know Your Customer (KYC)” cycles, CDNLive India has become a reliable event for the Technical Communications Engineering team to regularly touch base with customers, and to ensure the team knows their customers in order to exceed customer expectations.

The Publications Infrastructure and CPG…
- 4 Dec 2017
Breakfast Bytes: What's For Breakfast? Video Preview December 11th to 15th 2017

Paul McLellan

https://youtu.be/Ar98HS9Dnow Coming from Union Square, San Francisco (camera Carey Guo) Monday: COTS: Standard Products in US Government Electronics Tuesday: RISC-V Workshop, Milpitas Wednesday: Ploughing 1 TB of RAM with Twenty x86 Oxen a...
- 4 Dec 2017
SoC and IP: Book Your CES Meetings Now!

PaulaJones

Want to see the exciting technology that is behind some of the biggest innovations at CES? Book a meeting now to visit the Cadence invitation-only suites at CES 2018, January 9-12, South Hall 2, Suite MP2577 (same location as last year). See Tensilic...
- 4 Dec 2017
Breakfast Bytes: Formal Verification Sign-Off...and the First Text Message

Paul McLellan

Recently, it was the 10th annual Jasper User Group meeting (see my earlier post Jasper User Group 2017 for more background and a summary of the two best papers presented, at least as judged by the audience). There were also two invited pape...
- 4 Dec 2017
RF Engineering: How to Set Up and Plot Large-Signal S Parameters?

KamalKishore

Large-signal S-parameters (LSSPs) are an extension of small-signal S-parameters and are defined as the ratio of reflected (or transmitted) waves to incident waves.
- 4 Dec 2017
Verification: Perspec System Verifier is #1 in Portable Stimulus in 2017 User Survey

Steve Brown

It’s now official: Perspec System Verifier is rated the #1 product in the #1 category of Portable Stimulus, according to the 2017 EDA User Survey published on Deepchip.com. There were 33 user responses in favor of Perspec as the #1 tool, and dr...
- 1 Dec 2017
Breakfast Bytes: Silexica: Mastering Multicore

Paul McLellan

Since the invention of the microprocessor, it was a dream that it would be possible to build a really powerful computer by taking a lot of cheap simple computers and putting them together. This was especially a dream of hardware designers, who could ...
- 1 Dec 2017
Breakfast Bytes: Jasper User Group: How to Be a Formal Verification Lead

Paul McLellan

Recently, it was the 10th annual Jasper User Group meeting (see my earlier post Jasper User Group 2017 for more background, and a summary of the two "best" papers presented). There were also two invited papers. To open the first day, t...
- 30 Nov 2017
RF Engineering: Triple Beat Analysis: What, Why & How?

kmayank

The Triple Beat analysis is similar to Rapid IP2/IP3 analysis except that it uses three tones instead of two. It is used in cases where two closely-spaced small-signal inputs from a transmitter leak in to the receiver along with an intended small-signal RF input signal.
- 30 Nov 2017
The India Circuit: Hello, My Name Is Anna. Can I Help You?

Madhavi Rao

Chatbots are annoyingly familiar to anyone who has shopped online. The distracting little box on the bottom right of your screen saying chirpily, “Hello! My name is Anna. Can I help you?”. What I find most irritating is the fact that they...
- 29 Nov 2017
Verification: Check Again: Cadence Announces Release of the First PCIe 5.0 VIP—With TripleCheck!

XTeam

On November 28, 2017, Cadence announced the release of the first available PCIe® 5.0 Verification IP. This new VIP gives designers access to Cadence’s TripleCheck technology—which gives designers a comprehensive verification plan that uses measurable objectives related to spec features, along with a test suite containing thousands of tests. These combine to greatly improve the speed and quality of functional…
- 29 Nov 2017
Breakfast Bytes: Chips and Technologies: The First Fabless Company

Paul McLellan

As part of writing Fabless: the Transformation of the Semiconductor Industry a couple of years ago, I wanted to cover Chips and Technologies, which I believed was the first fabless semiconductor company. One of the founders was Dadao Banatao, no...
- 29 Nov 2017
Breakfast Bytes: November Breakfast Buffet

Paul McLellan

https://youtu.be/paqvuLll4pM Coming from the rain on the roof of Cadence building 10 (camera Sean) Rob Rutenbar Is Recipient of 2017 Kaufman Award Social Engineering Jasper User Group 2017 The Alto—Forty Years On Chips and Technologies: The Fi...
- 29 Nov 2017
Whiteboard Wednesdays: Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 1

References4U

In this week's Whiteboard Wednesday, Tom Hackett explains neural network basics using an Excel spreadsheet as a learning vehicle. You can download the spreadsheet here: https://ip.cadence.com/uploads/1213/neural-network-calculator-xlxs-zip

www.youtube.com/watch
- 28 Nov 2017
Breakfast Bytes: CCIX Update: TSMC, Xilinx, Cadence, Arm...and Jasper

Paul McLellan

CCIX (pronounced see-six) is the Cache Coherent Interconnect for Accelerators. I wrote about it in my post CCIX is Pronounced C6 and also when Cadence announced its collaboration with TSMC, Arm and Xilinx in Xilinx/Arm/Cadence/TSMC Announce Worl...
- 28 Nov 2017

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.