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Design&Reuse events are always exciting for their draw of an IP-centric audience. This year’s event was held in Bangalore, on April 6^th, and drew over 130 attendees. Experienced IP providers, fables IC vendors, external IP managers, internal reuse managers, foundries IP portfolio managers, IP market analysts, IP standard gurus. The scope of event is impressive, as represented by the breadth of presented concepts…

"Simulation Acceleration” or “Accelerated Verification”  are terms commonly used to describe  a verification environment in which the Device Under Test is synthesized and runs on the emulator, while the testbench runs on the simulator. This blog describes a technique for maximizing the performance of the simulator and thus increasing the overall performance of the Simulation Acceleration.

In Simulation…

In this week's Whiteboard Wednesdays video, Ofer Steinberg explains how accelerated VIP can dramatically speed up verification and describes a method to simplify the application of a SystemVerilog UVM test environment to simulation-acceleration with the Palladium XP platform.

www.youtube.com/watch

At CDNLive Silicon Valley, Geeta Garg and Chad Hale of ARM, and Ming Yue of Cadence reported on what it took to pull together a version of Innovus Implementation System and a version of the ARM physical library that would work cleanly at 10nm. They titled...

I talked to Uri Tal last week, who has just joined Cadence as a result of the Rocketick acquisition. Prior to the acquisition, he was Rocketick's CEO. He gave me a little history. Rocketick started development eight years ago. They have a product called...

Mike Demler gave the keynote at the Linley IoT conference a couple of weeks ago. He is a senior analyst there, and also a senior editor of Microprocessor Report and Mobile Chip Report. His background is in analog and mixed-signal design at companies like...

Every DAC, Heart of Technology (HOT) organizes an event. This year it will be held on Monday, June 6, from 7:30pm to 11:30pm at the Speakeasy (412 Congress Avenue). This year's event will be benefiting CASA of Travis County. Sponsors will have access...

As everyone in EDA knows, Denali threw a party at every DAC for what seems like forever. It is actually since 1999 which, in EDA years, is pretty much the same as forever. When Cadence acquired Denali in 2010, the first question everyone had was not ...

In this week's Whiteboard Wednesdays video, Liron Stoler describes how the Cadence Verification IP (VIP) modular architecture provides important benefits to users in block and system-level verification.

https://youtu.be/QZwPGmM9cBI

At CDNLive in Munich, Amjad Qureshi talked about High-Speed DDR and LPDDR Memory Sub-system Challenges. Amjad is Cadence's VP of R&D for memory interface IP, so he and his team have to live with these challenges every day.

Amjad started off...

Hello Spectre RF Users,

Next week is my all time favorite technical conference - the International Microwave Symposium IMS2016, May 22-27 in San Francisco, CA at the Moscone Center.

If you're at the conference, please stop by the Cadence booth and say...

Many of the security breaches that you read about are the results of software failures such as buffer overflow. But hardware is also vulnerable to attack. After Chris Eagle's keynote, the rest of the second day at EDPS was taken up with Jasper van...

A few weeks ago, Nest announced that it was shutting down Revolv. You probably don't have a Revolv product, a sort of smart-home hub. It contains seven radios and so speaks almost any protocol of any device you might have. It cost about $300. Nest acquired...

ADAS changes everything about automotive and requires a whole new range of skills in the automotive ecosystem that they have not had before: video and image processing, deep learning, high-bandwidth networking. One area that I hadn't really thought through...

Cadence is doing a lot at DAC as usual. Here is a summary. But read it carefully, because some things you can't leave to the last minute. You need to sign up or you may be disappointed. In particular, you must sign up for the Denali party and pick up...

In this week's Whiteboard Wednesdays video, Dennis Crespo discusses the significant enhancements to the Tensilica Vision P6 DSP for Convolutional Neural Networks (CNN).

https://youtu.be/R-tRjT7a5gw

CDNLive EMEA is nominally held in Munich (München in German) but, in fact, is held in a small town outside called Unterschleißheim at the Dolce Hotel. If you follow the directions we give, then you take the S-bahn (train) and then a bus. It suggests a...

The 16.6-2015 Design Entry HDL (DEHDL) release contains a few new capabilities!

Read on for more details…

Read-only Sheet Import
In Design Entry HDL (DEHDL), the sheet import command now supports the import of schematic sheets in read-only mode. For details, see the Importing Designs section in Allegro Design Entry HDL User Guide.

Component Browser - ADW Mode
You can now access the Component Browser in two modes…

One of the challenges of developing a new node is that there are a lot of moving parts that interact: the process, the design rules, the cell libraries, and the tools. At CDNLive in Munich, Luca Matti presented the work he is doing for N7 and N5. He is...

A couple of weeks ago, Silicon Catalyst organized an evening panel about corporate venture capital. Corporate VCs are groups within companies, perhaps Intel Capital is the most well-known, that make investments as opposed to the sort of VCs all along...

At CDNLive EMEA in Munich this week, there were two keynotes. The first was by Tom Beckley and was similar to the keynote that he presented at CDNLive Silicon Valley. You can read about it in my blog post. The second keynote was by Ulf Ewaldsson, the...

It is May already and just a month until DAC. I am sure that you already know that DAC is June 5-9^th in Austin. The DAC chair this year is Chuck Alpert, who works here at Cadence. He joined the company a couple of years ago after spending most of his...

In this week's Whiteboard Wednesdays video, Chris Rowen discusses the new Tensilica Vision P6 DSP from Cadence. The Vision P6 DSP is a major step forward in enhancing throughput and efficiency in vision DSP cores to target algorithms that require dramatic compute operations, like Convolutional Neural Networks (CNN).

It is the Embedded Vision Summit. Every year this event gets bigger, reflecting the growing interest in the area. Silicon is now capable enough that it is feasible to do complex algorithms in smartphones and automotive processors, rather than requiring...