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In this week's Whiteboard Wednesdays video, Charles Qi continues his discussion focused on technologies for the automotive industry. This week's topic highlights Cadence high-performance memory and interface IPs that address the challenges for memory and I/O bandwidth in automotive applications.

https://youtu.be/r47KnHPH6g8

The Allegro PCB Editor 16.6 Pastemask to Pastemask DRC now checks the ‘Package Geometry - Pastemask_Top’ shapes within the same symbol.

Read on for more details …

In Allegro PCB Editor, open a library symbol (e.g. pastemaskdrc.dra). Enable Pastemask DRC mode.

Setup – Constraints – Design Modes (Soldermask):

 

Open the Design Options (Soldermask) form and enter a value of 10 for Pastemask to…

The MIPI Alliance has developed dozens of specifications, standardizing all interfaces of mobile devices that are now part of almost any smartphone. If you are reading this blog through a mobile device (as you probably are...), the text and graphics you see on your screen went through the MIPI DSI interface, and the picture or video you took earlier with the phone’s camera was captured through the MIPI CSI interface and…

In this week's Whiteboard Wednesdays video, Charles Qi explains future automotive Ethernet networks and Cadence automotive Ethernet MAC IP.

https://youtu.be/Lao1EmUIuqE

In this week's Whiteboard Wednesday's video, the third in a three-part series, Pulin Desai discusses the criteria for selecting an imaging and vision processor engine for embedded applications.

https://youtu.be/fRybpm92DK8

The Incisive vManager tool for professional verification planning and management has now been officially released for almost two years. As demand for the Incisive vManager solution increases, so does our broad-scale support. Many of our users, however, are unaware of how much free training is actually available through Cadence as video content, available directly via Cadence Online Support (COS). This video content is…

The Allegro PCB Editor 16.6 ‘Replace Padstack’ command is now available as a context menu item when the selection set consists of mixed padstack instances.  Prior to 16.6, the selection set would have to be limited to common padstacks. This is available in General Edit Application mode.

Read on for more details …

The Options Panel now supports the ‘Ignore FIXED property’. The ‘Pin Number’ field has been…

In this week's Whiteboard Wednesday's video, Charles Qi discusses how Cadence scaleable DSP technology can help companies build products for automotive applications.

https://youtu.be/w7NWExhOSZg

In this week's Whiteboard Wednesdays video, the second in a two-part series, Charles Qi continues his discussion on the MIPI SoundWire standard. Charles talks about software design challenges and how customers can leverage Cadence design IP for the SoundWire protocol to effectively address these challenges.

https://youtu.be/jCz3b6ol1JA

Currently, user line width overrides are permitted during the Add Connect command, but are reset back to constraint driven when the command is completed. New behavior in the Allegro PCB Editor 16.6 release maintains the user setting until it is manually reset. The line width override now appears in blue, similar to the model established in the Constraint Manager Worksheets or shape parameter form to represent an override…

USB Type-C is an innovation that is transforming the electronics industry. What is significant about Type-C that demands attention? What should system architects consider for their future projects?

We sat down with MCCI Corporation’s CEO, Terrill Moore, to hear his thoughts on these questions. MCCI is a leading supplier of USB firmware and software, and actively participates in USB-IF standards activities. They are working…

In this week's Whiteboard Wednesdays video, Bob Salem provides a detailed overview of 802.11ad and how users can benefit from this latest wireless technology.

https://youtu.be/68ejrpHGhyo

Hi Everyone,

Last time, our Five-Minute Tutorial focused on the new Innovus Placement Optimization. The next step in the flow would be inserting clock trees. Now that we can take advantage of the CCOpt engine to create clock trees, we can also concurrently optimize for timing. But you still have the choice of whether or not to do so. This is a decision that could be design-dependent, and you may want to try both methods…

There is no other specification in the history of USB that caused so much discussion and interest as the USB Type-C. The new type of connector, designed to be a jack of all trades, eliminates all flaws of legacy Type-A and Type-B plugs, and adds significant benefits for USB and beyond. Here's a brief rundown of those benefits for those who are not frequent readers of the Cadence USB blog:

1. Reversible design: You…

In this week's Whiteboard Wednesdays, Charles Qi talks about the evolution of electronics in the automotive industry and the challenges and opportunities faced by suppliers today.

https://youtu.be/Ydd1UYy7jjc

There are a few NC Route enhancements in the 16.6 Allegro PCB Editor release.

Read on for more details …

Separate plated vs. non-plated files

An option has been added to the NC Route user interface to specify that separate output files are desired for plated versus non-plated routing. When this option is enabled, non-plated routing for both the board and slot holes will continue to be output to a ‘<name>.rou’ file…

In this week's Whiteboard Wednesdays video, Lou Ternullo provides a detailed overview of managed NAND flash devices and system design considerations.

https://youtu.be/L47Mcz8JLIw

Developing SoCs with high-speed memory interfaces, such as DDR4, presents substantial challenges throughout the design process. Today’s high-performance semiconductor processes enable high-speed design, and require expertise in signal integrity design, timing closure, and system bring-up. One of the biggest challenges is co-designing the memory interface, the chip package, and the PCB to preserve the high-speed signal…

Announcing Availability of ONFI 4.0 IP

Flash memory applications have expanded from USB Flash Drive “sticks” to solid state drives (SSD) and beyond, as designers demand increased non-volatile storage capacity and performance. Designers are also faced with the challenge to reduce system-level power. To meet these needs Cadence is unveiling its Open NAND Flash Interface (ONFI) 4.0 IP, delivering increased data access rates…

The 16.6 Allegro PCB Editor ‘DRC by Window’ command is an alternative to running DRC update at the full design level. As the name suggests, the command is limited to checking the elements within the extents of a user-defined selection window. On large, highly constrained designs where database performance is problematic, one can simply disable ‘On-line’ DRC mode if favor of this ‘On-demand’ method. …